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ORCIDKubilay Atasu
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2020 – today
- 2024
[c27]Béni Egressy, Luc von Niederhäusern, Jovan Blanusa, Erik R. Altman, Roger Wattenhofer, Kubilay Atasu
:
Provably Powerful Graph Neural Networks for Directed Multigraphs. AAAI 2024: 11838-11846- [i11]Jovan Blanusa, Maximo Cravero Baraja, Andreea Anghel, Luc von Niederhäusern, Erik R. Altman, Haris Pozidis, Kubilay Atasu:
Graph Feature Preprocessor: Real-time Extraction of Subgraph-based Features from Transaction Graphs. CoRR abs/2402.08593 (2024) - 2023
- [j15]Jovan Blanusa, Kubilay Atasu, Paolo Ienne:
Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-constrained Cycles. ACM Trans. Parallel Comput. 10(3): 15:1-15:35 (2023) - [c26]Erik R. Altman, Jovan Blanusa, Luc von Niederhäusern, Beni Egressy, Andreea Anghel, Kubilay Atasu:
Realistic Synthetic Financial Transactions for Anti-Money Laundering Models. NeurIPS 2023 - [i10]Jovan Blanusa, Kubilay Atasu, Paolo Ienne:
Fast Parallel Algorithms for Enumeration of Simple, Temporal, and Hop-Constrained Cycles. CoRR abs/2301.01068 (2023) - [i9]Béni Egressy, Luc von Niederhäusern, Jovan Blanusa, Erik R. Altman, Roger Wattenhofer, Kubilay Atasu:
Provably Powerful Graph Neural Networks for Directed Multigraphs. CoRR abs/2306.11586 (2023) - [i8]Erik R. Altman, Béni Egressy, Jovan Blanusa, Kubilay Atasu:
Realistic Synthetic Financial Transactions for Anti-Money Laundering Models. CoRR abs/2306.16424 (2023) - 2022
- [c25]Jovan Blanusa, Paolo Ienne, Kubilay Atasu:
Scalable Fine-Grained Parallel Cycle Enumeration Algorithms. SPAA 2022: 247-258 - [i7]Jovan Blanusa, Paolo Ienne, Kubilay Atasu:
Scalable Fine-Grained Parallel Cycle Enumeration Algorithms. CoRR abs/2202.09685 (2022) - 2020
- [j14]Thomas P. Parnell, Celestine Dünner, Kubilay Atasu, Manolis Sifalakis, Haralampos Pozidis:
Tera-scale coordinate descent on GPUs. Future Gener. Comput. Syst. 108: 1173-1191 (2020) - [j13]Jovan Blanusa, Radu Stoica, Paolo Ienne, Kubilay Atasu:
Many-Core Clique Enumeration with Fast Set Intersections. Proc. VLDB Endow. 13(11): 2676-2690 (2020) - [c24]Jovan Blanusa, Radu Stoica, Paolo Ienne, Kubilay Atasu:
Parallelizing Maximal Clique Enumeration on Modern Manycore Processors. IPDPS Workshops 2020: 211-214
2010 – 2019
- 2019
- [j12]Michail Vlachos, Celestine Dünner, Reinhard Heckel, Vassilios G. Vassiliadis, Thomas P. Parnell, Kubilay Atasu:
Addressing Interpretability and Cold-Start in Matrix Factorization for Recommender Systems. IEEE Trans. Knowl. Data Eng. 31(7): 1253-1266 (2019) - [c23]Kubilay Atasu, Thomas Mittelholzer:
Linear-Complexity Data-Parallel Earth Mover's Distance Approximations. ICML 2019: 364-373 - 2018
- [j11]Raphael Polig, Kubilay Atasu, Heiner Giefers, Christoph Hagleitner, Laura Chiticariu, Frederick Reiss, Huaiyu Zhu, H. Peter Hofstee:
A hardware compilation framework for text analytics queries. J. Parallel Distributed Comput. 111: 260-272 (2018) - [i6]Raphael Polig, Kubilay Atasu, Laura Chiticariu, Christoph Hagleitner, H. Peter Hofstee, Frederick R. Reiss, Eva Sitaridi, Huaiyu Zhu:
Giving Text Analytics a Boost. CoRR abs/1806.01103 (2018) - [i5]Kubilay Atasu, Thomas Mittelholzer:
Low-Complexity Data-Parallel Earth Mover's Distance Approximations. CoRR abs/1812.02091 (2018) - [i4]Kubilay Atasu, Vasileios Vasileiadis, Michail Vlachos:
Faster Text Similarity Using a Linear-Complexity Relaxed Word Mover's Distance. ERCIM News 2018(112) (2018) - 2017
- [j10]Steven Derrien, Kubilay Atasu, João M. P. Cardoso, Jürgen Becker:
Foreword to the Special Section on Reconfigurable Computing. J. Signal Process. Syst. 88(2): 103-105 (2017) - [c22]Celestine Dünner, Thomas P. Parnell, Kubilay Atasu, Manolis Sifalakis, Haralampos Pozidis:
Understanding and optimizing the performance of distributed machine learning applications on apache spark. IEEE BigData 2017: 331-338 - [c21]Kubilay Atasu, Thomas P. Parnell, Celestine Dünner, Manolis Sifalakis, Haralampos Pozidis, Vasileios Vasileiadis, Michail Vlachos, Cesar Berrospi, Abdel Labbi:
Linear-complexity relaxed word Mover's distance with GPU acceleration. IEEE BigData 2017: 889-896 - [c20]Kubilay Atasu, Thomas P. Parnell, Celestine Dünner, Michail Vlachos, Haralampos Pozidis:
High-Performance Recommender System Training Using Co-Clustering on CPU/GPU Clusters. ICPP 2017: 372-381 - [c19]Thomas P. Parnell, Celestine Dünner, Kubilay Atasu, Manolis Sifalakis, Haris Pozidis:
Large-Scale Stochastic Learning Using GPUs. IPDPS Workshops 2017: 419-428 - [i3]Thomas P. Parnell, Celestine Dünner, Kubilay Atasu, Manolis Sifalakis, Haris Pozidis:
Large-Scale Stochastic Learning using GPUs. CoRR abs/1702.07005 (2017) - [i2]Kubilay Atasu, Thomas P. Parnell, Celestine Dünner, Manolis Sifalakis, Haralampos Pozidis, Vasileios Vasileiadis, Michail Vlachos, Cesar Berrospi, Abdel Labbi:
Linear-Complexity Relaxed Word Mover's Distance with GPU Acceleration. CoRR abs/1711.07227 (2017) - 2016
- [j9]Kubilay Atasu:
Feature-rich Regular Expression Matching Accelerator for Text Analytics. J. Signal Process. Syst. 85(3): 355-371 (2016) - [c18]Raphael Polig, Kubilay Atasu, Christoph Hagleitner, Theresa Xu, Akihiro Nakayama:
Annotation-based finite-state transducers on reconfigurable devices. FPL 2016: 1-9 - [i1]Celestine Dünner, Thomas P. Parnell, Kubilay Atasu, Manolis Sifalakis, Haralampos Pozidis:
High-Performance Distributed Machine Learning using Apache SPARK. CoRR abs/1612.01437 (2016) - 2015
- [c17]Kubilay Atasu:
Leftmost longest regular expression matching in reconfigurable logic. FPT 2015: 17-23 - 2014
- [j8]Raphael Polig, Kubilay Atasu, Laura Chiticariu, Christoph Hagleitner, H. Peter Hofstee, Frederick R. Reiss, Huaiyu Zhu, Eva Sitaridi:
Giving Text Analytics a Boost. IEEE Micro 34(4): 6-14 (2014) - [j7]Melissa C. Smith, Kubilay Atasu:
Guest Editorial: Application Specific Processors and Architectures. J. Signal Process. Syst. 77(1-2): 1-3 (2014) - [c16]Kubilay Atasu:
Resource-efficient regular expression matching architecture for text analytics. ASAP 2014: 1-8 - [c15]Raphael Polig, Kubilay Atasu, Heiner Giefers, Laura Chiticariu:
Compiling text analytics queries to FPGAs. FPL 2014: 1-6 - [c14]Raphael Polig, Kubilay Atasu, Christoph Hagleitner, Laura Chiticariu, Frederick Reiss, Huaiyu Zhu, H. Peter Hofstee:
Hardware-accelerated text analytics. Hot Chips Symposium 2014: 1-24 - 2013
- [j6]Kubilay Atasu, Raphael Polig, Jonathan Rohrer, Christoph Hagleitner:
Exploring the design space of programmable regular expression matching accelerators. J. Syst. Archit. 59(10-D): 1184-1196 (2013) - [c13]Kubilay Atasu, Raphael Polig, Christoph Hagleitner, Frederick R. Reiss:
Hardware-accelerated regular expression matching for high-throughput text analytics. FPL 2013: 1-7 - [c12]Raphael Polig, Kubilay Atasu, Christoph Hagleitner:
Token-based dictionary pattern matching for text analytics. FPL 2013: 1-6 - [c11]Kubilay Atasu, Florian Dörfler, Jan van Lunteren, Christoph Hagleitner:
Hardware-Accelerated Regular Expression Matching with Overlap Handling on IBM PowerEN Processor. IPDPS 2013: 1254-1265 - 2012
- [j5]Kubilay Atasu, Wayne Luk, Oskar Mencer, Can C. Özturan, Günhan Dündar:
FISH: Fast Instruction SyntHesis for Custom Processors. IEEE Trans. Very Large Scale Integr. Syst. 20(1): 52-65 (2012) - [j4]Joseph Reddington, Kubilay Atasu:
Complexity of Computing Convex Subgraphs in Custom Instruction Synthesis. IEEE Trans. Very Large Scale Integr. Syst. 20(12): 2337-2341 (2012) - [c10]Mitra Purandare, Kubilay Atasu, Christoph Hagleitner:
Proving correctness of regular expression accelerators. DAC 2012: 350-355 - [c9]Jan van Lunteren, Christoph Hagleitner, Timothy Heil, Giora Biran, Uzi Shvadron, Kubilay Atasu:
Designing a Programmable Wire-Speed Regular-Expression Matching Accelerator. MICRO 2012: 461-472
2000 – 2009
- 2009
- [c8]Jonathan Rohrer, Kubilay Atasu, Jan van Lunteren, Christoph Hagleitner:
Memory-efficient distribution of regular expressions for fast deep packet inspection. CODES+ISSS 2009: 147-154 - 2008
- [j3]Kubilay Atasu, Can C. Özturan, Günhan Dündar, Oskar Mencer, Wayne Luk:
CHIPS: Custom Hardware Instruction Processor Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(3): 528-541 (2008) - [c7]Kubilay Atasu, Oskar Mencer, Wayne Luk, Can C. Özturan, Günhan Dündar:
Fast custom instruction identification by convex subgraph enumeration. ASAP 2008: 1-6 - 2007
- [b1]Kubilay Atasu:
Hardware/software partitioning for custom instruction processors (Özelleştirilebilir komut kümeli işlemciler için yazılım/donanım bölüştürmesi). Boğaziçi University, Turkey, 2007 - [c6]Kubilay Atasu, Robert G. Dimond, Oskar Mencer, Wayne Luk, Can C. Özturan, Günhan Dündar:
Optimizing instruction-set extensible processors under data bandwidth constraints. DATE 2007: 588-593 - 2006
- [j2]Laura Pozzi, Kubilay Atasu, Paolo Ienne:
Exact and approximate algorithms for the extension of embedded processor instruction sets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(7): 1209-1229 (2006) - [c5]Wayne Luk, Kubilay Atasu, Robert G. Dimond, Oskar Mencer:
Towards optimal custom instruction processors. Hot Chips Symposium 2006: 1-23 - 2005
- [c4]Kubilay Atasu, Günhan Dündar, Can C. Özturan:
An integer linear programming approach for identifying instruction-set extensions. CODES+ISSS 2005: 172-177 - 2004
- [c3]Partha Biswas, Vinay Choudhary, Kubilay Atasu, Laura Pozzi, Paolo Ienne, Nikil D. Dutt:
Introduction of local memory elements in instruction set extensions. DAC 2004: 729-734 - [c2]Kubilay Atasu, Luca Breveglieri, Marco Macchetti:
Efficient AES implementations for ARM based platforms. SAC 2004: 841-845 - 2003
- [j1]Kubilay Atasu, Laura Pozzi, Paolo Ienne:
Automatic Application-Specific Instruction-Set Extensions Under Microarchitectural Constraints. Int. J. Parallel Program. 31(6): 411-428 (2003) - [c1]Kubilay Atasu, Laura Pozzi, Paolo Ienne:
Automatic application-specific instruction-set extensions under microarchitectural constraints. DAC 2003: 256-261
Coauthor Index
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last updated on 2024-10-07 21:18 CEST by the dblp team
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