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Journal Articles
- 2020
[j16]Zhiwei Xu, Sangjin Byun
:
A Poly Resistor Based Time Domain CMOS Temperature Sensor with 9b SAR and Fine Delay Line. Sensors 20(7): 2053 (2020)- [j15]Sangjin Byun:
Categorization and Characterization of Time Domain CMOS Temperature Sensors. Sensors 20(22): 6700 (2020) - 2017
- [j14]Sangjin Byun:
Analysis and Verification of DLL-Based GFSK Demodulator Using Multiple-IF-Period Delay Line. IEEE Trans. Circuits Syst. II Express Briefs 64-II(1): 6-10 (2017) - [j13]Chung Hwan Son, Sangjin Byun:
On Frequency Detection Capability of Full-Rate Linear and Binary Phase Detectors. IEEE Trans. Circuits Syst. II Express Briefs 64-II(7): 757-761 (2017) - 2016
- [j12]Sangjin Byun:
1∼3 GHz VCO with rail-to-rail VCONT range. IEICE Electron. Express 13(11): 20160373 (2016) - [j11]Sangjin Byun:
0.97 mW/Gb/s, 4 Gb/s CMOS clock and data recovery IC with dynamic voltage scaling. IET Circuits Devices Syst. 10(3): 220-228 (2016) - [j10]Sangjin Byun:
A 400 Mb/s∼2.5 Gb/s Referenceless CDR IC Using Intrinsic Frequency Detection Capability of Half-Rate Linear Phase Detector. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(10): 1592-1604 (2016) - 2014
- [j9]Sangjin Byun:
Analysis and Design of CMOS Received Signal Strength Indicator. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(10): 2970-2977 (2014) - 2013
- [j8]Sangjin Byun, Chung Hwan Son, Jongil Hwang, Byung-Hun Min, Mun-Yang Park, Hyun-Kyu Yu:
1-5.6 Gb/s CMOS clock and data recovery IC with a static phase offset compensated linear phase detector. IET Circuits Devices Syst. 7(3) (2013) - 2012
- [j7]Sangjin Byun, Chung Hwan Son, Jae Joon Kim:
Simple odd number frequency divider with 50% duty cycle. IEICE Electron. Express 9(15): 1249-1253 (2012) - 2011
- [j6]Jae Joon Kim, Chang-Hyuk Cho, Kwan-Yeob Chae, Sangjin Byun:
A low-power/high-resolution dual-mode analog-to-digital converter for wireless sensor applications. IEICE Electron. Express 8(20): 1730-1735 (2011) - 2010
- [j5]Sangjin Byun, Jae Hoon Shim:
Charge Pump circuit with wide range digital leakage current mismatch compensator. IEICE Electron. Express 7(23): 1709-1713 (2010) - 2008
- [j4]Byung-Guk Kim, Lee-Sup Kim, Sangjin Byun, Hyun-Kyu Yu:
A 20 Gb/s 1: 4 DEMUX Without Inductors and Low-Power Divide-by-2 Circuit in 0.13 µm CMOS Technology. IEEE J. Solid State Circuits 43(2): 541-549 (2008) - 2006
- [j3]Sangjin Byun, Jyung Chan Lee, Jae Hoon Shim, Kwangjoon Kim, Hyun-Kyu Yu:
A 10-Gb/s CMOS CDR and DEMUX IC With a Quarter-Rate Linear Phase Detector. IEEE J. Solid State Circuits 41(11): 2566-2576 (2006) - 2005
- [j2]Jinwook Kim, Jeongsik Yang, Sangjin Byun, Hyunduk Jun, Jeongkyu Park, Cormac S. G. Conroy, Beomsup Kim:
A four-channel 3.125-Gb/s/ch CMOS serial-link transceiver with a mixed-mode adaptive equalizer. IEEE J. Solid State Circuits 40(2): 462-471 (2005) - 2003
- [j1]Sangjin Byun, Chan-Hong Park, Yongchul Song, Sung-Ho Wang, Cormac S. G. Conroy, Beomsup Kim:
A low-power CMOS Bluetooth RF transceiver with a digital offset canceling DLL-based GFSK demodulator. IEEE J. Solid State Circuits 38(10): 1609-1618 (2003)
Conference and Workshop Papers
- 2024
- [c4]Yoomi Park, Sangjin Byun:
An 884MHz, -41.8dBm Input Power Sensitivity, 570-Stage CMOS RF-DC Rectifier With Ground Shielded Input Coupling Capacitors. ISCAS 2024: 1-5 - 2006
- [c3]Sangjin Byun, Jyung Chan Lee, Jae Hoon Shim, Kwangjoon Kim, Hyun-Kyu Yu:
A 10Gb/s CMOS CDR and DEMUX IC with a Quarter-Rate Linear Phase Detector. ISSCC 2006: 1324-1333 - [c2]Byung-Guk Kim, Lee-Sup Kim, Sangjin Byun, Hyun-Kyu Yu:
A 20gb/s 1: 4 DEMUX without inductors in 0.13µm CMOS. ISSCC 2006: 2152-2159 - 1999
- [c1]Tae Hun Kim, Jeongsik Yang, Kyoo Hyun Lim, Jin Wook Kim, Jeong Eun Lee, Hyoung Sik Nam, Young Gon Kim, Jeong Pyo Kim, Sangjin Byun, Bae Sung Kwon, Beomsup Kim:
16-bit DSP and System for Baseband / Voiceband Processing of IS-136 Cellular Telephony. ASP-DAC 1999: 49-
Coauthor Index
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