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Jose Luis Nunes

José Luís Nunes

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2010 – 2019

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2016
[c6]
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Jose Luis Nunes, João Carlos Cunha, Mário Zenha Rela:
On the Effects of Cumulative SEUs in FPGA-Based Systems. EDCC 2016: 89-96
[c5]
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Jose Luis Nunes, João Carlos Cunha, Mário Zenha Rela:
Using Failure Prediction to Improve FPGA Scrubbing. LADC 2016: 135-138
[i1]
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Jose Luis Nunes:
Improving FPGA resilience through Partial Dynamic Reconfiguration. CoRR abs/1608.06559 (2016)
2015
[c4]
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Jose Luis Nunes, Tamas Pecserke, João Carlos Cunha, Mário Zenha Rela:
FIRED - Fault Injector for Reconfigurable Embedded Devices. PRDC 2015: 1-10
2013
[c3]
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Jose Luis Nunes:
Improving the dependability of FPGA-based real-time embedded systems with partial dynamic reconfiguration. DSN Workshops 2013: 1-4
[c2]
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Jose Luis Nunes, João Carlos Cunha, Raul Barbosa, Mário Zenha Rela:
Evaluating Xilinx SEU Controller Macro for fault injection. DSN 2013: 1-2
2011
[c1]
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José Luís Nunes, João Carlos Cunha, Raul Barbosa, Mário Zenha Rela:
Using partial dynamic FPGA reconfiguration to support real-time dependability. EWDC 2011: 107-108

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