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S. Kala
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2020 – today
- 2023
- [j4]M. A. Muneeb, Nalesh S, S. Kala:
A physically unclonable function architecture with multiple responses on FPGA. Int. J. Embed. Syst. 16(1): 67-74 (2023) - [c13]Noble G, Nalesh S, S. Kala:
Bit-Flip Attack Detection for Secure Sparse Matrix Computations on FPGA. APCCAS 2023: 65-69 - [c12]Abhinav Kalvacherla, Rachana George, Nalesh S, S. Kala:
Approximate CNN on FPGA Using Toom-Cook Multiplier. iSES 2023: 271-276 - [c11]Noble G, Nalesh S, S. Kala:
MOSCON: Modified Outer Product based Sparse Matrix-Matrix Multiplication Accelerator with Configurable Tiles. VLSID 2023: 264-269 - 2022
- [c10]Vishnu Bajjuri, Nalesh S, Sree Ranjani Rajendran, S. Kala:
Adiabatic Physical Unclonable Function Using Cross-Coupled Pair. iSES 2022: 278-282 - 2021
- [c9]Mahesh M, Nalesh S, S. Kala:
Bandwidth-Efficient Sparse Matrix Multiplier Architecture for Deep Neural Networks on FPGA. SoCC 2021: 7-12 - [c8]Mahesh Mahadurkar, Nalesh Sivanandan, S. Kala:
Hardware Acceleration of SpMV Multiplier for Deep Learning. VDAT 2021: 1-6
2010 – 2019
- 2019
- [j3]S. Kala
, Jimson Mathew, Babita R. Jose, Nalesh Sivanandan:
Radix-43 based two-dimensional FFT architecture with efficient data reordering scheme. IET Comput. Digit. Tech. 13(2): 78-86 (2019) - [j2]S. Kala
, Babita R. Jose, Jimson Mathew, Nalesh Sivanandan:
High-Performance CNN Accelerator on FPGA Using Unified Winograd-GEMM Architecture. IEEE Trans. Very Large Scale Integr. Syst. 27(12): 2816-2828 (2019) - [c7]S. Kala, Babita R. Jose, Jimson Mathew, Nalesh Sivanandan:
Efficient Hardware Acceleration of Convolutional Neural Networks. SoCC 2019: 191-192 - [c6]S. Kala, Jimson Mathew, Babita R. Jose, Nalesh Sivanandan:
UniWiG: Unified Winograd-GEMM Architecture for Accelerating CNN on FPGAs. VLSID 2019: 209-214 - 2018
- [c5]S. Kala, Nalesh Sivanandan, Babita R. Jose, Jimson Mathew, Marco Ottavi
:
Two dimensional FFT architecture based on radix-43 algorithm with efficient output reordering. DTIS 2018: 1-2 - [c4]S. Kala, Debdeep Paul, Babita R. Jose, Nalesh Sivanandan:
Design Space Exploration of Convolution Algorithms to Accelerate CNNs on FPGA. ISED 2018: 21-25 - [c3]S. Kala, Babita R. Jose, Debdeep Paul, Jimson Mathew:
A Hardware Accelerator for Convolutional Neural Network Using Fast Fourier Transform. VDAT 2018: 28-36 - 2015
- [j1]S. Kala, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan:
Scalable and Energy Efficient, Dynamically Reconfigurable Fast Fourier Transform Architecture. J. Low Power Electron. 11(3): 426-435 (2015) - 2014
- [c2]S. Kala, Nalesh Sivanandan, S. K. Nandy, Ranjani Narayan:
Energy Efficient, Scalable, and Dynamically Reconfigurable FFT Architecture for OFDM Systems. ISED 2014: 20-24 - 2013
- [c1]S. Kala, Nalesh Sivanandan, Arka Maity, S. K. Nandy, Ranjani Narayan:
High throughput, low latency, memory optimized 64K point FFT architecture using novel radix-4 butterfly unit. ISCAS 2013: 3034-3037
Coauthor Index
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