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ORCIDYitao Ma
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- affiliation: Tohoku University, Japan
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Journal Articles
- 2023
[j11]Tao Li
, Yitao Ma, Tetsuo Endoh:
Neuromorphic processor-oriented hybrid Q-format multiplication with adaptive quantization for tiny YOLO3. Neural Comput. Appl. 35(15): 11013-11041 (2023)- [j10]Tao Li, Yitao Ma, Tetsuo Endoh:
From Algorithm to Module: Adaptive and Energy-Efficient Quantization Method for Edge Artificial Intelligence in IoT Society. IEEE Trans. Ind. Informatics 19(8): 8953-8964 (2023) - [j9]Tao Li, Yitao Ma, Ko Yoshikawa, Tetsuo Endoh:
Corrections to "Hybrid Signed Convolution Module With Unsigned Divide-and-Conquer Multiplier for Energy-Efficient STT-MRAM-Based AI Accelerator". IEEE Trans. Very Large Scale Integr. Syst. 31(6): 906 (2023) - [j8]Tao Li, Yitao Ma, Ko Yoshikawa, Tetsuo Endoh:
Hybrid Signed Convolution Module With Unsigned Divide-and-Conquer Multiplier for Energy-Efficient STT-MRAM-Based AI Accelerator. IEEE Trans. Very Large Scale Integr. Syst. 31(7): 1078-1082 (2023) - 2022
- [j7]Tao Li, Yitao Ma, Ko Yoshikawa, Osamu Nomura, Tetsuo Endoh:
Energy-Efficient Convolution Module With Flexible Bit-Adjustment Method and ADC Multiplier Architecture for Industrial IoT. IEEE Trans. Ind. Informatics 18(5): 3055-3065 (2022) - 2021
- [j6]Masanori Natsui, Akira Tamakoshi, Hiroaki Honjo, Toshinari Watanabe, Takashi Nasuno, Chaoliang Zhang, Takaho Tanigawa, Hirofumi Inoue, Masaaki Niwa, Toru Yoshiduka, Yasuo Noguchi, Mitsuo Yasuhira, Yitao Ma, Hui Shen, Shunsuke Fukami, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu:
Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition. IEEE J. Solid State Circuits 56(4): 1116-1128 (2021) - 2020
- [j5]Tao Li, Yitao Ma, Tetsuo Endoh:
Normalization-Based Validity Index of Adaptive K-Means Clustering for Multi-Solution Application. IEEE Access 8: 9403-9419 (2020) - [j4]Tao Li, Yitao Ma, Tetsuo Endoh:
A Systematic Study of Tiny YOLO3 Inference: Toward Compact Brainware Processor With Less Memory and Logic Gate. IEEE Access 8: 142931-142955 (2020) - [j3]Tao Li, Yitao Ma, Hui Shen, Tetsuo Endoh:
FPGA Implementation of Real-Time Pedestrian Detection Using Normalization-Based Validation of Adaptive Features Clustering. IEEE Trans. Veh. Technol. 69(9): 9330-9341 (2020) - 2019
- [j2]Masanori Natsui, Daisuke Suzuki, Akira Tamakoshi, Toshinari Watanabe, Hiroaki Honjo, Hiroki Koike, Takashi Nasuno, Yitao Ma, Takaho Tanigawa, Yasuo Noguchi, Mitsuo Yasuhira, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu:
A 47.14-µW 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications. IEEE J. Solid State Circuits 54(11): 2991-3004 (2019) - 2016
- [j1]Takahiro Hanyu, Tetsuo Endoh, Daisuke Suzuki, Hiroki Koike, Yitao Ma, Naoya Onizawa, Masanori Natsui, Shoji Ikeda, Hideo Ohno:
Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing. Proc. IEEE 104(10): 1844-1863 (2016)
Conference and Workshop Papers
- 2020
- [c4]Masanori Natsui, Akira Tamakoshi, Hiroaki Honjo, Toshinari Watanabe, Takashi Nasuno, Chaoliang Zhang, Takaho Tanigawa, Hirofumi Inoue, Masaaki Niwa, Toru Yoshiduka, Yasuo Noguchi, Mitsuo Yasuhira, Yitao Ma, Hui Shen, Shunsuke Fukami, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu:
Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage. VLSI Circuits 2020: 1-2 - 2019
- [c3]Masanori Natsui, Daisuke Suzuki, Akira Tamakoshi, Toshinari Watanabe, Hiroaki Honjo, Hiroki Koike, Takashi Nasuno, Yitao Ma, Takaho Tanigawa, Yasuo Noguchi, Mitsuo Yasuhira, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu:
An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz. ISSCC 2019: 202-204 - 2013
- [c2]Yitao Ma, Tadashi Shibata, Tetsuo Endoh:
An MTJ-based nonvolatile associative memory architecture with intelligent power-saving scheme for high-speed low-power recognition applications. ISCAS 2013: 1248-1251 - 2011
- [c1]Yitao Ma, Tetsuo Endoh, Tadashi Shibata:
A vertical-MOSFET-based digital core circuit for high-speed low-power vector matching. ISOCC 2011: 203-206
Coauthor Index
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