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ORCIDDan Nicolaescu
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2010 – 2019
- 2011
[c10]Chris Rowen, Dan Nicolaescu, Rajiv Ravindran, David Heine, Grant Martin, James Kim, Dror E. Maydan, Nupur Andrews, Bill Huffman, Vakis Papaparaskeva, Shay Gal-On, Peter R. Nuth, Pushkar Patwardhan, Manish Paradkar:
The world's fastest DSP core: Breaking the 100 GMAC/s barrier. Hot Chips Symposium 2011: 1-25
2000 – 2009
- 2006
- [c9]Dan Nicolaescu, Babak Salamat, Alexander V. Veidenbaum:
Fast Speculative Address Generation and Way Caching for Reducing L1 Data Cache Energy. ICCD 2006: 101-107 - 2005
- [c8]Dan Nicolaescu, Alexander V. Veidenbaum, Alexandru Nicolau:
Using a Way Cache to Improve Performance of Set-Associative Caches. ISHPC 2005: 93-104 - 2004
- [c7]Juan L. Aragón
, Dan Nicolaescu, Alexander V. Veidenbaum, Ana-Maria Badulescu:
Energy-Efficient Design for Highly Associative Instruction Caches in Next-Generation Embedded Processors. DATE 2004: 1374-1375 - [c6]Alexander V. Veidenbaum, Dan Nicolaescu:
Low Energy, Highly-Associative Cache Design for Embedded Processors. ICCD 2004: 332-335 - [c5]Dan Nicolaescu, Alexander V. Veidenbaum, Alexandru Nicolau:
Caching Values in the Load Store Queue. MASCOTS 2004: 580-587 - 2003
- [c4]Dan Nicolaescu, Alexander V. Veidenbaum, Alexandru Nicolau:
Reducing Power Consumption for High-Associativity Data Caches in Embedded Processors. DATE 2003: 11064-11069 - [c3]Dan Nicolaescu, Alexander V. Veidenbaum, Alexandru Nicolau:
Reducing data cache energy consumption via cached load/store queue. ISLPED 2003: 252-257 - [p1]Dan Nicolaescu, Alexander V. Veidenbaum, Alex Nicolau:
Low Energy Associative Data Caches for Embedded Systems. Embedded Software for SoC 2003: 513-525 - 2000
- [c2]Dan Nicolaescu, Xiaomei Ji, Alexander V. Veidenbaum, Alexandru Nicolau, Rajesh K. Gupta:
Compiler-Directed Cache Line Size Adaptivity. Intelligent Memory Systems 2000: 183-187 - [c1]Xiaomei Ji, Dan Nicolaescu, Alexander V. Veidenbaum, Alexandru Nicolau, Rajesh K. Gupta:
Compiler-Directed Cache Assist Adaptivity. ISHPC 2000: 88-104
Coauthor Index
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