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Li-Ming Denq

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2010 – 2019

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2012
[c9]
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Chun-Chuan Chi, Yung-Fa Chou, Ding-Ming Kwai, Yu-Ying Hsiao, Cheng-Wen Wu, Yu-Tsao Hsing, Li-Ming Denq, Tsung-Hsiang Lin:
3D-IC BISR for stacked memories using cross-die spares. VLSI-DAT 2012: 1-4
2011
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Mincent Lee, Li-Ming Denq, Cheng-Wen Wu:
A Memory Built-In Self-Repair Scheme Based on Configurable Spares. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(6): 919-929 (2011)
[c8]
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Chin-Fu Li, Chi-Ying Lee, Chen-Hsing Wang, Shu-Lin Chang, Li-Ming Denq, Chun-Chuan Chi, Hsuan-Jung Hsu, Ming-Yi Chu, Jing-Jia Liou, Shi-Yu Huang, Po-Chiun Huang, Hsi-Pin Ma, Jenn-Chyou Bor, Cheng-Wen Wu, Ching-Cheng Tien, Chi-Hu Wang, Yung-Sheng Kuo, Chih-Tsun Huang, Tien-Yu Chang:
A low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testing. DAC 2011: 771-776
2010
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Yu-Tsao Hsing, Li-Ming Denq, Chao-Hsun Chen, Cheng-Wen Wu:
Economic Analysis of the HOY Wireless Test Methodology. IEEE Des. Test Comput. 27(3): 20-30 (2010)
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Chih-Yen Lo, Yu-Tsao Hsing, Li-Ming Denq, Cheng-Wen Wu:
SOC Test Architecture and Method for 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(10): 1645-1649 (2010)

2000 – 2009

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2009
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Li-Ming Denq, Yu-Tsao Hsing, Cheng-Wen Wu:
Hybrid BIST Scheme for Multiple Heterogeneous Embedded Memories. IEEE Des. Test Comput. 26(2): 64-73 (2009)
2008
[c7]
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Chun-Kai Hsu, Li-Ming Denq, Mao-Yin Wang, Jing-Jia Liou, Chih-Tsun Huang, Cheng-Wen Wu:
Area and Test Cost Reduction for On-Chip Wireless Test Channels with System-Level Design Techniques. ATS 2008: 245-250
2007
[c6]
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Li-Ming Denq, Cheng-Wen Wu:
A Hybrid BIST Scheme for Multiple Heterogeneous Embedded Memories. ATS 2007: 349-354
[c5]
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Jing-Jia Liou, Chih-Tsun Huang, Cheng-Wen Wu, Ching-Cheng Tien, Chi-Hu Wang, Hsi-Pin Ma, Ying-Yen Chen, Yueh-Chih Hsu, Li-Ming Denq, Chien-Jung Chiu, Young-Wey Li, Chieh-Ming Chang:
A prototype of a wireless-based test system. SoCC 2007: 225-228
2006
[c4]
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Li-Ming Denq, Tzu-chiang Wang, Cheng-Wen Wu:
An Enhanced SRAM BISR Design with Reduced Timing Penalty. ATS 2006: 25-30
2004
[c3]
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Kuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Chih-Yen Lo, Li-Ming Denq, Chih-Tsun Huang, Shin-Wei Hung, Jye-Yuan Lee:
An SOC Test Integration Platform and Its Industrial Realization. ITC 2004: 1213-1222
[c2]
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Li-Ming Denq, Rei-Fu Huang, Cheng-Wen Wu, Yeong-Jar Chang, Wen Ching Wu:
A Parallel Built-in Diagnostic Scheme for Multiple Embedded Memories. MTDT 2004: 65-69
2003
[c1]
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Rei-Fu Huang, Li-Ming Denq, Cheng-Wen Wu, Jin-Fu Li:
A Testability-Driven Optimizer and Wrapper Generator for Embedded Memories. MTDT 2003: 53-

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