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Sungwoo Kim
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2020 – today
- 2023
- [c14]Seunghwan Sung, Sujin Hur, Sungwoo Kim, Dongho Ha, Yunho Oh, Won Woo Ro:
MAD MAcce: Supporting Multiply-Add Operations for Democratizing Matrix-Multiplication Accelerators. MICRO 2023: 367-379 - [c13]Hyunwuk Lee, Hyungjun Jang, Sungbin Kim, Sungwoo Kim, Wonho Cho, Won Woo Ro:
Exploiting Inherent Properties of Complex Numbers for Accelerating Complex Valued Neural Networks. MICRO 2023: 1121-1134 - [c12]Kyungtae Kim, Sungwoo Kim, Kevin R. B. Butler, Antonio Bianchi, Rick Kennell, Dave Tian:
Fuzz The Power: Dual-role State Guided Black-box Fuzzing for USB Power Delivery. USENIX Security Symposium 2023: 5845-5861 - 2022
- [j12]Hyojun Kim, Woosong Jung, Kwandong Kim, Sungwoo Kim, Woo-Seok Choi, Deog-Kyoon Jeong:
A Low-Jitter 8-GHz RO-Based ADPLL With PVT-Robust Replica-Based Analog Closed Loop for Supply Noise Compensation. IEEE J. Solid State Circuits 57(6): 1712-1722 (2022) - [j11]Moon-Chul Choi, Sanghee Lee, Seungha Roh, Kwangho Lee, Jonghyun Oh, Sungwoo Kim, Kwandong Kim, Woo-Seok Choi, Jaeha Kim, Deog-Kyoon Jeong:
A 2.5-32 Gb/s Gen 5-PCIe Receiver With Multi-Rate CDR Engine and Hybrid DFE. IEEE Trans. Circuits Syst. II Express Briefs 69(6): 2677-2681 (2022) - [c11]Sungwoo Kim, Gisu Yeo, Taegyu Kim, Junghwan John Rhee, Yuseok Jeon, Antonio Bianchi, Dongyan Xu, Dave (Jing) Tian:
ShadowAuth: Backward-Compatible Automatic CAN Authentication for Legacy ECUs. AsiaCCS 2022: 534-545 - 2021
- [j10]Min-Seong Choo, Sungwoo Kim, Han-Gon Ko, Sung-Yong Cho, Kwanseo Park, Jinhyung Lee, Soyeong Shin, Hankyu Chi, Deog-Kyoon Jeong:
A PVT Variation-Robust All-Digital Injection-Locked Clock Multiplier With Real-Time Offset Tracking Using Time-Division Dual Calibration. IEEE J. Solid State Circuits 56(8): 2525-2538 (2021)
2010 – 2019
- 2019
- [j9]Youngchul Shin, Sungwoo Kim, Ilkyeong Moon:
Integrated optimal scheduling of repair crew and relief vehicle after disaster. Comput. Oper. Res. 105: 237-247 (2019) - [j8]Sungwoo Kim, Ilkyeong Moon:
Traveling Salesman Problem With a Drone Station. IEEE Trans. Syst. Man Cybern. Syst. 49(1): 42-52 (2019) - [c10]Jeongho Hwang, Hyungrok Do, Hong-Seok Choi, Gyu-Seob Jeong, Daehyun Koh, Sungwoo Kim, Deog-Kyoon Jeong:
56Gb/s PAM-4 VCSEL Transmitter with Quarter-Rate Forwarded Clock using 65nm CMOS Circuits. OFC 2019: 1-3 - [c9]Jeongho Hwang, Hong-Seok Choi, Hyungrok Do, Gyu-Seob Jeong, Daehyun Koh, Kwanseo Park, Sungwoo Kim, Deog-Kyoon Jeong:
A 64Gb/s 2.29pJ/b PAM-4 VCSEL Transmitter With 3-Tap Asymmetric FFE in 65nm CMOS. VLSI Circuits 2019: 268- - 2018
- [j7]Sung-Yong Cho, Sungwoo Kim, Min-Seong Choo, Han-Gon Ko, Jinhyung Lee, Woo-Rham Bae, Deog-Kyoon Jeong:
A 2.5-5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(9): 2691-2702 (2018) - 2017
- [j6]Jeongsoo Lim, In-Ho Lee, Inwook Shim, Hyobin Jung, Hyunmin Joe, Hyoin Bae, Okkee Sim, Jaesung Oh, Taejin Jung, Seunghak Shin, Kyungdon Joo, Mingeuk Kim, Kang Kyu Lee, Yunsu Bok, Dong-Geol Choi, Cho Buyoun, Sungwoo Kim, Jungwoo Heo, Inhyeok Kim, Jungho Lee, In So Kweon, Jun-Ho Oh:
Robot System of DRC-HUBO+ and Control Strategy of Team KAIST in DARPA Robotics Challenge Finals. J. Field Robotics 34(4): 802-829 (2017) - [j5]Kwanseo Park, Jinhyung Lee, Kwangho Lee, Min-Seong Choo, Sungchun Jang, Sang-Hyeok Chu, Sungwoo Kim, Deog-Kyoon Jeong:
A 55.1 mW 1.62-to-8.1 Gb/s Video Interface Receiver Generating up to 680 MHz Stream Clock Over 20 dB Loss Channel. IEEE Trans. Circuits Syst. II Express Briefs 64-II(12): 1432-1436 (2017) - [c8]Sungwoo Kim, Young Soo Park, Kihyun Lee, Ilkyeong Moon:
Repair Crew Scheduling Considering Variable Disaster Aspects. APMS (1) 2017: 57-63 - [c7]Sungwoo Kim, Han-Gon Ko, Sung-Yong Cho, Jinhyung Lee, Soyeong Shin, Min-Seong Choo, Hankyu Chi, Deog-Kyoon Jeong:
29.7 A 2.5GHz injection-locked ADPLL with 197fsrms integrated jitter and -65dBc reference spur using time-division dual calibration. ISSCC 2017: 494-495 - 2016
- [j4]Gyu-Seob Jeong, Sang-Hyeok Chu, Yoonsoo Kim, Sungchun Jang, Sungwoo Kim, Woo-Rham Bae, Sung-Yong Cho, Haram Ju, Deog-Kyoon Jeong:
A 20 Gb/s 0.4 pJ/b Energy-Efficient Transmitter Driver Utilizing Constant- Gm Bias. IEEE J. Solid State Circuits 51(10): 2312-2327 (2016) - [c6]Jinhyung Lee, Sungwoo Kim, Min-Seong Choo, Sung-Yong Cho, Han-Gon Ko, Deog-Kyoon Jeong:
A theoretical analysis of phase shift in pulse injection-locked oscillators. ISCAS 2016: 1662-1665 - 2015
- [j3]Sang-Hyeok Chu, Woo-Rham Bae, Gyu-Seob Jeong, Sungchun Jang, Sungwoo Kim, Jiho Joo, Gyungock Kim, Deog-Kyoon Jeong:
A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process. IEEE J. Solid State Circuits 50(11): 2603-2612 (2015) - [j2]Sungchun Jang, Sungwoo Kim, Sang-Hyeok Chu, Gyu-Seob Jeong, Yoonsoo Kim, Deog-Kyoon Jeong:
An Optimum Loop Gain Tracking All-Digital PLL Using Autocorrelation of Bang-Bang Phase-Frequency Detection. IEEE Trans. Circuits Syst. II Express Briefs 62-II(9): 836-840 (2015) - [c5]Gyu-Seob Jeong, Sang-Hyeok Chu, Yoonsoo Kim, Sungchun Jang, Sungwoo Kim, Woo-Rham Bae, Sung-Yong Cho, Haram Ju, Deog-Kyoon Jeong:
A 20 Gb/s 0.4 pJ/b energy-efficient transmitter driver architecture utilizing constant Gm. A-SSCC 2015: 1-4 - [c4]Sung-Yong Cho, Sungwoo Kim, Min-Seong Choo, Jinhyung Lee, Han-Gon Ko, Sungchun Jang, Sang-Hyeok Chu, Woo-Rham Bae, Yoonsoo Kim, Deog-Kyoon Jeong:
A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection. ESSCIRC 2015: 384-387 - [c3]Sungwoo Kim, Sungchun Jang, Jun-Eun Park, Yoonsoo Kim, Gyungock Kim, Deog-Kyoon Jeong:
A compact 22-Gb/s transmitter for optical links with all-digital phase-locked loop. ISCAS 2015: 2856-2859 - [c2]Jun-Eun Park, Yoonsoo Kim, Sungwoo Kim, Gyungock Kim, Deog-Kyoon Jeong:
20-Gb/s 3.6-VPP-swing source-series-terminated driver with 2-Tap FFE in 65-nm CMOS. ISCAS 2015: 2864-2867 - [c1]Sungchun Jang, Sungwoo Kim, Sang-Hyeok Chu, Gyu-Seob Jeong, Yoonsoo Kim, Deog-Kyoon Jeong:
An all-digital bang-bang PLL using two-point modulation and background gain calibration for spread spectrum clock generation. VLSIC 2015: 136- - 2014
- [j1]Taeho Kim, Sungchun Jang, Sungwoo Kim, Sang-Hyeok Chu, Jiheon Park, Deog-Kyoon Jeong:
A Four-Channel 32-Gb/s Transceiver With Current-Recycling Output Driver and On-Chip AC Coupling in 65-nm CMOS Process. IEEE Trans. Circuits Syst. II Express Briefs 61-II(5): 304-308 (2014)
Coauthor Index
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