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ORCIDNuwan Jayasena
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2020 – today
- 2024
[c29]Suchita Pati
, Shaizeen Aga, Mahzabeen Islam, Nuwan Jayasena, Matthew D. Sinclair:
T3: Transparent Tracking & Triggering for Fine-grained Overlap of Compute & Collectives. ASPLOS (2) 2024: 1146-1164- [i7]Suchita Pati, Shaizeen Aga, Mahzabeen Islam, Nuwan Jayasena, Matthew D. Sinclair:
T3: Transparent Tracking & Triggering for Fine-grained Overlap of Compute & Collectives. CoRR abs/2401.16677 (2024) - [i6]Suchita Pati, Shaizeen Aga, Nuwan Jayasena, Matthew D. Sinclair:
Global Optimizations & Lightweight Dynamic Logic for Concurrency. CoRR abs/2409.02227 (2024) - 2023
- [c28]Suchita Pati, Shaizeen Aga, Mahzabeen Islam, Nuwan Jayasena, Matthew D. Sinclair:
Tale of Two Cs: Computation vs. Communication Scaling for Future Transformers on Future Hardware. IISWC 2023: 140-153 - [c27]Gabriel H. Loh, Michael J. Schulte, Mike Ignatowski, Vignesh Adhinarayanan, Shaizeen Aga, Derrick Aguren, Varun Agrawal, Ashwin M. Aji, Johnathan Alsop, Paul T. Bauman, Bradford M. Beckmann, Majed Valad Beigi, Sergey Blagodurov, Travis Boraten, Michael Boyer, William C. Brantley, Noel Chalmers, Shaoming Chen, Kevin Cheng, Michael L. Chu, David Cownie, Nicholas Curtis, Joris Del Pino, Nam Duong, Alexandru Dutu, Yasuko Eckert, Christopher Erb, Chip Freitag, Joseph L. Greathouse, Sudhanva Gurumurthi, Anthony Gutierrez, Khaled Hamidouche, Sachin Hossamani, Wei Huang, Mahzabeen Islam, Nuwan Jayasena, John Kalamatianos, Onur Kayiran, Jagadish Kotra, Alan Lee, Daniel Lowell, Niti Madan, Abhinandan Majumdar, Nicholas Malaya, Srilatha Manne, Susumu Mashimo, Damon McDougall, Elliot Mednick, Michael Mishkin, Mark Nutter, Indrani Paul, Matthew Poremba, Brandon Potter, Kishore Punniyamurthy, Sooraj Puthoor, Steven E. Raasch, Karthik Rao, Gregory Rodgers, Marko Scrbak, Mohammad Seyedzadeh, John Slice, Vilas Sridharan, René van Oostrum, Eric Van Tassell, Abhinav Vishnu, Samuel Wasmundt, Mark Wilkening, Noah Wolfe, Mark Wyse, Adithya Yalavarti, Dmitri Yudanov:
A Research Retrospective on AMD's Exascale Computing Journey. ISCA 2023: 81:1-81:14 - [i5]Suchita Pati, Shaizeen Aga, Mahzabeen Islam, Nuwan Jayasena, Matthew D. Sinclair:
Computation vs. Communication Scaling for Future Transformers on Future Hardware. CoRR abs/2302.02825 (2023) - [i4]Johnathan Alsop, Shaizeen Aga, Mohamed Assem Ibrahim, Mahzabeen Islam, Andrew McCrabb, Nuwan Jayasena:
Inclusive-PIM: Hardware-Software Co-design for Broad Acceleration on Commercial PIM Architectures. CoRR abs/2309.07984 (2023) - 2022
- [c26]Suchita Pati, Shaizeen Aga, Nuwan Jayasena, Matthew D. Sinclair:
Demystifying BERT: System Design Implications. IISWC 2022: 296-309 - 2021
- [i3]Suchita Pati, Shaizeen Aga, Nuwan Jayasena, Matthew D. Sinclair:
Demystifying BERT: Implications for Accelerator Design. CoRR abs/2104.08335 (2021) - 2020
- [j6]Alex D. Breslow, Nuwan Jayasena:
Morton filters: fast, compressed sparse cuckoo filters. VLDB J. 29(2-3): 731-754 (2020) - [c25]Suchita Pati, Shaizeen Aga, Matthew D. Sinclair, Nuwan Jayasena:
SeqPoint: Identifying Representative Iterations of Sequence-Based Neural Networks. ISPASS 2020: 69-80 - [c24]Nuwan Jayasena:
Memory Performance Optimization. IA3@SC 2020: ix - [i2]Suchita Pati, Shaizeen Aga, Matthew D. Sinclair, Nuwan Jayasena:
SeqPoint: Identifying Representative Iterations of Sequence-based Neural Networks. CoRR abs/2007.10459 (2020)
2010 – 2019
- 2019
- [c23]Shaizeen Aga, Nuwan Jayasena, Mike Ignatowski:
Co-ML: a case for <u>co</u>llaborative <u>ML</u> acceleration using near-data processing. MEMSYS 2019: 506-517 - 2018
- [j5]Alexander Dodd Breslow, Nuwan Jayasena:
Morton Filters: Faster, Space-Efficient Cuckoo Filters via Biasing, Compression, and Decoupled Logical Sparsity. Proc. VLDB Endow. 11(9): 1041-1055 (2018) - [j4]Hyojong Kim, Ramyad Hadidi, Lifeng Nai, Hyesoon Kim, Nuwan Jayasena, Yasuko Eckert, Onur Kayiran, Gabriel H. Loh:
CODA: Enabling Co-location of Computation and Data for Multiple GPU Systems. ACM Trans. Archit. Code Optim. 15(3): 32:1-32:23 (2018) - [c22]Farzad Khorasani, Hodjat Asghari Esfeden, Amin Farmahini Farahani, Nuwan Jayasena, Vivek Sarkar:
RegMutex: Inter-Warp GPU Register Time-Sharing. ISCA 2018: 816-828 - 2017
- [j3]Marko Scrbak, Mahzabeen Islam, Krishna M. Kavi, Mike Ignatowski, Nuwan Jayasena:
Exploring the Processing-in-Memory design space. J. Syst. Archit. 75: 59-67 (2017) - [c21]Mahzabeen Islam, Krishna M. Kavi, Mitesh R. Meswani, Soumik Banerjee, Nuwan Jayasena:
HBM-Resident Prefetching for Heterogeneous Memory System. ARCS 2017: 124-136 - [c20]Marko Scrbak, Joseph L. Greathouse, Nuwan Jayasena, Krishna M. Kavi:
DVFS Space Exploration in Power Constrained Processing-in-Memory Systems. ARCS 2017: 221-233 - [c19]Andreas Prodromou, Mitesh R. Meswani, Nuwan Jayasena, Gabriel H. Loh, Dean M. Tullsen:
MemPod: A Clustered Architecture for Efficient and Scalable Migration in Flat Address Space Multi-level Memories. HPCA 2017: 433-444 - [i1]Hyojong Kim, Ramyad Hadidi, Lifeng Nai, Hyesoon Kim, Nuwan Jayasena, Yasuko Eckert, Onur Kayiran, Gabriel H. Loh:
CODA: Enabling Co-location of Computation and Data for Near-Data Processing. CoRR abs/1710.09517 (2017) - 2016
- [j2]Babak Falsafi, Mircea Stan, Kevin Skadron, Nuwan Jayasena, Yunji Chen, Jinhua Tao, Ravi Nair, Jaime H. Moreno, Naveen Muralimanohar, Karthikeyan Sankaralingam, Cristian Estan:
Near-Memory Data Services. IEEE Micro 36(1): 6-13 (2016) - [c18]Reena Panda, Yasuko Eckert, Nuwan Jayasena, Onur Kayiran, Michael Boyer, Lizy Kurian John:
Prefetching Techniques for Near-memory Throughput Processors. ICS 2016: 40:1-40:14 - [c17]Lifan Xu, Dong Ping Zhang, Nuwan Jayasena, John Cavazos:
HADM: Hybrid Analysis for Detection of Malware. IntelliSys (2) 2016: 702-724 - [c16]Paula Aguilera, Dong Ping Zhang, Nam Sung Kim, Nuwan Jayasena:
Fine-Grained Task Migration for Graph Algorithms Using Processing in Memory. IPDPS Workshops 2016: 489-498 - [c15]Amin Farmahini Farahani, David Roberts, Nuwan Jayasena:
Analytical Study on Bandwidth Efficiency of Heterogeneous Memory Systems. MEMSYS 2016: 104-118 - [c14]Alex D. Breslow, Dong Ping Zhang, Joseph L. Greathouse, Nuwan Jayasena, Dean M. Tullsen:
Horton Tables: Fast Hash Tables for In-Memory Data-Intensive Computing. USENIX ATC 2016: 281-294 - 2015
- [j1]Michael J. Schulte, Mike Ignatowski, Gabriel H. Loh, Bradford M. Beckmann, William C. Brantley, Sudhanva Gurumurthi, Nuwan Jayasena, Indrani Paul, Steven K. Reinhardt, Gregory Rodgers:
Achieving Exascale Capabilities through Heterogeneous Computing. IEEE Micro 35(4): 26-36 (2015) - [c13]Marko Scrbak, Mahzabeen Islam, Krishna M. Kavi, Mike Ignatowski, Nuwan Jayasena:
Processing-in-Memory: Exploring the Design Space. ARCS 2015: 43-54 - [c12]Manish Arora, Srilatha Manne, Indrani Paul, Nuwan Jayasena, Dean M. Tullsen:
Understanding idle behavior and power gating mechanisms in the context of modern benchmarks on CPU-GPU Integrated systems. HPCA 2015: 366-377 - [c11]Gene Y. Wu, Joseph L. Greathouse, Alexander Lyashevsky, Nuwan Jayasena, Derek Chiou:
GPGPU performance and power estimation using machine learning. HPCA 2015: 564-576 - 2014
- [c10]Mahzabeen Islam, Marko Scrbak, Krishna M. Kavi, Mike Ignatowski, Nuwan Jayasena:
Improving Node-Level MapReduce Performance Using Processing-in-Memory Technologies. Euro-Par Workshops (2) 2014: 425-437 - [c9]Dong Ping Zhang, Nuwan Jayasena, Alexander Lyashevsky, Joseph L. Greathouse, Lifan Xu, Michael Ignatowski:
TOP-PIM: throughput-oriented programmable processing in memory. HPDC 2014: 85-98 - [c8]Niladrish Chatterjee, Mike O'Connor, Gabriel H. Loh, Nuwan Jayasena, Rajeev Balasubramonian:
Managing DRAM Latency Divergence in Irregular GPGPU Applications. SC 2014: 128-139 - [c7]Manish Arora, Srilatha Manne, Yasuko Eckert, Indrani Paul, Nuwan Jayasena, Dean M. Tullsen:
A comparison of core power gating strategies implemented in modern hardware. SIGMETRICS 2014: 559-560 - 2013
- [c6]Michael Boyer, Kevin Skadron, Shuai Che, Nuwan Jayasena:
Load balancing in a changing world: dealing with heterogeneity and performance variability. Conf. Computing Frontiers 2013: 21:1-21:10 - [c5]Dong Ping Zhang, Nuwan Jayasena, Alexander Lyashevsky, Joseph L. Greathouse, Mitesh R. Meswani, Mark Nutter, Mike Ignatowski:
A new perspective on processing-in-memory architecture design. MSPC@PLDI 2013: 7:1-7:3
2000 – 2009
- 2005
- [c4]Mattan Erez, Nuwan Jayasena, Timothy J. Knight, William J. Dally:
Fault Tolerance Techniques for the Merrimac Streaming Supercomputer. SC 2005: 29 - 2004
- [c3]Nuwan Jayasena, Mattan Erez, Jung Ho Ahn, William J. Dally:
Stream Register Files with Indexed Access. HPCA 2004: 60-72 - 2003
- [c2]William J. Dally, Francois Labonte, Abhishek Das, Pat Hanrahan, Jung Ho Ahn, Jayanth Gummaraju, Mattan Erez, Nuwan Jayasena, Ian Buck, Timothy J. Knight, Ujval J. Kapasi:
Merrimac: Supercomputing with Streams. SC 2003: 35 - 2000
- [c1]Ken Mai, Tim Paaske, Nuwan Jayasena, Ron Ho, William J. Dally, Mark Horowitz:
Smart Memories: a modular reconfigurable architecture. ISCA 2000: 161-171
Coauthor Index
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last updated on 2024-10-07 21:18 CEST by the dblp team
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