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ORCIDKhalid Javeed
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2020 – today
- 2024
[j16]Khalid Javeed
, Fadi N. Sibai, Ali El-Moursy:
A Compact and Low Latency SPM Architecture for ECC Cryptosystems. IEEE Access 12: 147552-147563 (2024)- [j15]Saeed Iqbal, Adnan N. Qureshi, Musaed A. Alhussein, Khursheed Aurangzeb, Khalid Javeed, Rizwan Ali Naqvi:
Privacy-preserving collaborative AI for distributed deep learning with cross-sectional data. Multim. Tools Appl. 83(33): 80051-80073 (2024) - [j14]Khalid Javeed, Ali El-Moursy, David Gregg:
E2CSM: efficient FPGA implementation of elliptic curve scalar multiplication over generic prime field GF(p). J. Supercomput. 80(1): 50-74 (2024) - [c6]Yasir Ali Shah, Ciara Rafferty, Ayesha Khalid, Safiullah Khan, Khalid Javeed, Máire O'Neill:
Efficient Soft Core Multiplier for Post Quantum Digital Signatures. ISCAS 2024: 1-5 - 2023
- [j13]Khalid Javeed, Ali El-Moursy, David Gregg:
EC-Crypto: Highly Efficient Area-Delay Optimized Elliptic Curve Cryptography Processor. IEEE Access 11: 56649-56662 (2023) - [j12]Abeer Iftikhar, Kashif Naseer Qureshi, Ali A. Altalbe, Khalid Javeed:
Security Provision by Using Detection and Prevention Methods to Ensure Trust in Edge-Based Smart City Networks. IEEE Access 11: 137529-137547 (2023) - [j11]Adil Hussain, Kashif Naseer Qureshi, Khalid Javeed, Musaed A. Alhussein:
An Enhanced Intelligent Intrusion Detection System to Secure E-Commerce Communication Systems. Comput. Syst. Sci. Eng. 47(2): 2513-2528 (2023) - [j10]Khalid Javeed, Ali El-Moursy:
Area-time efficient point multiplication architecture on twisted Edwards curve over general prime field G F ( p ). Int. J. Circuit Theory Appl. 51(12): 5962-5979 (2023) - [c5]Khalid Javeed:
FPGA Implementation of Area-Time Aware ECC Scalar Multiplication Core. ICECS 2023: 1-4 - 2022
- [j9]Khalid Javeed, Kamran Saeed, David Gregg:
High-speed parallel reconfigurable Fp multipliers for elliptic curve cryptography applications. Int. J. Circuit Theory Appl. 50(4): 1160-1173 (2022) - 2020
- [j8]Yasir Ali Shah, Khalid Javeed, Muhammad Imran Shehzad, Shoaib Azmat:
LUT-based high-speed point multiplier for Goldilocks-Curve448. IET Comput. Digit. Tech. 14(4): 149-157 (2020)
2010 – 2019
- 2019
- [j7]Zeeshan Haider, Khalid Javeed, Mei Song, Xiaojun Wang:
A Low-Cost Self-Test Architecture Integrated With PRESENT Cipher Core. IEEE Access 7: 46045-46058 (2019) - [j6]Yasir Ali Shah, Khalid Javeed, Shoaib Azmat, Xiaojun Wang:
Redundant-Signed-Digit-Based High Speed Elliptic Curve Cryptographic Processor. J. Circuits Syst. Comput. 28(5): 1950081:1-1950081:33 (2019) - 2018
- [j5]Yasir Ali Shah, Khalid Javeed, Shoaib Azmat, Xiaojun Wang:
A high-speed RSD-based flexible ECC processor for arbitrary curves over general prime field. Int. J. Circuit Theory Appl. 46(10): 1858-1878 (2018) - [j4]Safiullah Khan, Khalid Javeed, Yasir Ali Shah:
High-speed FPGA implementation of full-word Montgomery multiplier for ECC applications. Microprocess. Microsystems 62: 91-101 (2018) - 2017
- [j3]Khalid Javeed, Xiaojun Wang:
Low latency flexible FPGA implementation of point multiplication on elliptic curves over GF(p). Int. J. Circuit Theory Appl. 45(2): 214-228 (2017) - [j2]Khalid Javeed, Xiaojun Wang, Mike Scott:
High performance hardware support for elliptic curve cryptography over general prime field. Microprocess. Microsystems 51: 331-342 (2017) - 2016
- [j1]Khalid Javeed, Xiaojun Wang:
FPGA Based High Speed SPA Resistant Elliptic Curve Scalar Multiplier Architecture. Int. J. Reconfigurable Comput. 2016: 6371403:1-6371403:10 (2016) - [c4]Khalid Javeed, Daniel Irwin, Xiaojun Wang:
Design and Performance Comparison of Modular Multipliers Implemented on FPGA Platform. ICCCS (1) 2016: 251-260 - [i1]Khalid Javeed, Xiaojun Wang:
Speed and Area Optimized Parallel Higher-Radix Modular Multipliers. IACR Cryptol. ePrint Arch. 2016: 53 (2016) - 2015
- [c3]Khalid Javeed, Xiaojun Wang, Mike Scott:
Serial and parallel interleaved modular multipliers on FPGA platform. FPL 2015: 1-4 - 2014
- [c2]Khalid Javeed, Xiaojun Wang:
Efficient montgomery multiplier for pairing and elliptic curve based cryptography. CSNDSP 2014: 255-260 - [c1]Khalid Javeed, Xiaojun Wang:
Radix-4 and radix-8 booth encoded interleaved modular multipliers over general Fp. FPL 2014: 1-6
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last updated on 2024-11-07 20:34 CET by the dblp team
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