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2020 – today
- 2024
[j8]Tianchen Gu
, Wangzhen Li, Aidong Zhao, Zhaori Bi, Xudong Li, Fan Yang, Changhao Yan, Wenchuang Walter Hu, Dian Zhou, Tao Cui, Xin Liu, Zaikun Zhang, Xuan Zeng:
BBGP-sDFO: Batch Bayesian and Gaussian Process Enhanced Subspace Derivative Free Optimization for High-Dimensional Analog Circuit Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(2): 417-430 (2024)- [j7]Zhaoting Chen, Junzhe Cai, Changhao Yan, Zhaori Bi, Yuzhe Ma, Bei Yu, Wenchuang Walter Hu, Dian Zhou, Xuan Zeng:
pNeurFill: Enhanced Neural Network Model-Based Dummy Filling Synthesis With Perimeter Adjustment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(2): 667-680 (2024) - [j6]Aidong Zhao, Tianchen Gu, Zhaori Bi, Fan Yang, Changhao Yan, Xuan Zeng, Zixiao Lin, Wenchuang Walter Hu, Dian Zhou:
D3PBO: Dynamic Domain Decomposition-based Parallel Bayesian Optimization for Large-scale Analog Circuit Sizing. ACM Trans. Design Autom. Electr. Syst. 29(3): 44:1-44:25 (2024) - [c9]Ruiyu Lyu, Yuan Meng, Aidong Zhao, Zhaori Bi, Keren Zhu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng:
A Study on Exploring and Exploiting the High-dimensional Design Space for Analog Circuit Design Automation : (Invited Paper). ASPDAC 2024: 671-678 - [c8]Xuyang Zhao, Zhaori Bi, Changhao Yan, Fan Yang, Ye Lu, Dian Zhou, Xuan Zeng:
Asynchronous Batch Constrained Multi-Objective Bayesian Optimization for Analog Circuit Sizing. ASPDAC 2024: 872-877 - [c7]Tianchen Gu, Jiaqi Wang, Zhaori Bi, Changhao Yan, Fan Yang, Yajie Qin, Tao Cui, Xuan Zeng:
tSS-BO: Scalable Bayesian Optimization for Analog Circuit Sizing via Truncated Subspace Sampling. DATE 2024: 1-6 - [c6]Yuan Meng, Ruiyu Lyu, Zhaori Bi, Changhao Yan, Fan Yang, Wenchuang Hu, Dian Zhou, Xuan Zeng:
Circuits Physics Constrained Predictor of Static IR Drop with Limited Data. DATE 2024: 1-2 - [i1]Jintao Li, Haochang Zhi, Ruiyu Lyu, Wangzhen Li, Zhaori Bi, Keren Zhu, Yanhan Zeng, Weiwei Shan, Changhao Yan, Fan Yang, Yun Li, Xuan Zeng:
AnalogGym: An Open and Practical Testing Suite for Analog Circuit Synthesis. CoRR abs/2409.08534 (2024) - 2023
- [j5]Biao He, Shuhan Zhang, Yifan Wang, Tianning Gao, Fan Yang, Changhao Yan, Dian Zhou, Zhaori Bi, Xuan Zeng:
A Batched Bayesian Optimization Approach for Analog Circuit Synthesis via Multi-Fidelity Modeling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(2): 347-359 (2023) - [c5]Aidong Zhao, Xianan Wang, Zixiao Lin, Zhaori Bi, Xudong Li, Changhao Yan, Fan Yang, Li Shang, Dian Zhou, Xuan Zeng:
cVTS: A Constrained Voronoi Tree Search Method for High Dimensional Analog Circuit Synthesis. DAC 2023: 1-6 - 2022
- [j4]Yifan Wang, Zhaori Bi, Yuxue Xie, Tao Wu, Xuan Zeng, Shuang Chen, Dian Zhou:
Learning From Highly Confident Samples for Automatic Knee Osteoarthritis Severity Assessment: Data From the Osteoarthritis Initiative. IEEE J. Biomed. Health Informatics 26(3): 1239-1250 (2022) - [c4]Jingyao Zhao, Changhao Yan, Zhaori Bi, Fan Yang, Xuan Zeng, Dian Zhou:
A Novel and Efficient Bayesian Optimization Approach for Analog Designs with Multi-Testbench. ASP-DAC 2022: 86-91 - [c3]Xu Fu, Changhao Yan, Zhaori Bi, Fan Yang, Dian Zhou, Xuan Zeng:
A Batch Bayesian Optimization Approach For Analog Circuit Synthesis Based On Multi-Points Selection Criterion. ISCAS 2022: 2886-2890
2010 – 2019
- 2018
- [j3]Yishi Yang, Hengliang Zhu, Zhaori Bi, Changhao Yan, Dian Zhou, Yangfeng Su, Xuan Zeng:
Smart-MSP: A Self-Adaptive Multiple Starting Point Optimization Approach for Analog Circuit Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(3): 531-544 (2018) - 2017
- [j2]Zhaori Bi, Dian Zhou, Sheng-Guo Wang, Xuan Zeng:
Optimization and Quality Estimation of Circuit Design via Random Region Covering Method. ACM Trans. Design Autom. Electr. Syst. 23(1): 1:1-1:25 (2017) - 2015
- [j1]Liuxi Qian, Zhaori Bi, Dian Zhou, Xuan Zeng:
Automated Technology Migration Methodology for Mixed-Signal Circuit Based on Multistart Optimization Framework. IEEE Trans. Very Large Scale Integr. Syst. 23(11): 2595-2605 (2015) - [c2]Minghua Li, Zhaori Bi, Dian Zhou, Xuan Zeng:
Analog circuit performance bound estimation based on extreme value theory. MWSCAS 2015: 1-4 - 2013
- [c1]Zhaori Bi, Wei Li, Dian Zhou, Xuan Zeng, Sheng-Guo Wang:
Mixed-signal system verification by SystemC/SystemC-AMS and HSIM-VCS in near field communication tag design. ASICON 2013: 1-4
Coauthor Index
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last updated on 2024-10-14 23:28 CEST by the dblp team
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