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2020 – today
- 2023
[c9]Kevin Laeufer, Vighnesh Iyer, David Biancolin, Jonathan Bachrach, Borivoje Nikolic, Koushik Sen:
Simulator Independent Coverage for RTL Hardware Languages. ASPLOS (3) 2023: 606-615- 2021
- [j4]David Biancolin
, Albert Magyar, Sagar Karandikar, Alon Amid, Borivoje Nikolic, Jonathan Bachrach, Krste Asanovic:
Accessible, FPGA Resource-Optimized Simulation of Multiclock Systems in FireSim. IEEE Micro 41(4): 58-66 (2021) - 2020
- [j3]Alon Amid, David Biancolin, Abraham Gonzalez, Daniel Grubb, Sagar Karandikar, Harrison Liew, Albert Magyar, Howard Mao, Albert J. Ou, Nathan Pemberton, Paul Rigge, Colin Schmidt, John Charles Wright, Jerry Zhao, Yakun Sophia Shao, Krste Asanovic, Borivoje Nikolic:
Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs. IEEE Micro 40(4): 10-21 (2020) - [c8]Alon Amid, David Biancolin, Abraham Gonzalez, Daniel Grubb, Sagar Karandikar, Harrison Liew, Albert Magyar, Howard Mao, Albert J. Ou, Nathan Pemberton, Paul Rigge, Colin Schmidt, John Charles Wright, Jerry Zhao, Jonathan Bachrach, Yakun Sophia Shao, Borivoje Nikolic, Krste Asanovic:
Invited: Chipyard - An Integrated SoC Research and Implementation Environment. DAC 2020: 1-6
2010 – 2019
- 2019
- [j2]Sagar Karandikar, Howard Mao, Donggyu Kim, David Biancolin, Alon Amid, Dayeol Lee, Nathan Pemberton, Emmanuel Amaro, Colin Schmidt, Aditya Chopra, Qijing Huang, Kyle Kovacs, Borivoje Nikolic, Randy Howard Katz, Jonathan Bachrach, Krste Asanovic:
FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud. IEEE Micro 39(3): 56-65 (2019) - [c7]David Biancolin, Sagar Karandikar, Donggyu Kim, Jack Koenig, Andrew Waterman, Jonathan Bachrach, Krste Asanovic:
FASED: FPGA-Accelerated Simulation and Evaluation of DRAM. FPGA 2019: 330-339 - [c6]Albert Magyar, David Biancolin, John Koenig, Sanjit Seshia, Jonathan Bachrach, Krste Asanovic:
Golden Gate: Bridging The Resource-Efficiency Gap Between ASICs and FPGA Prototypes. ICCAD 2019: 1-8 - 2018
- [c5]Donggyu Kim, Christopher Celio, Sagar Karandikar, David Biancolin, Jonathan Bachrach, Krste Asanovic:
DESSERT: Debugging RTL Effectively with State Snapshotting for Error Replays across Trillions of Cycles. FPL 2018: 76-80 - [c4]Sagar Karandikar, Howard Mao, Donggyu Kim, David Biancolin, Alon Amid, Dayeol Lee, Nathan Pemberton, Emmanuel Amaro, Colin Schmidt, Aditya Chopra, Qijing Huang, Kyle Kovacs, Borivoje Nikolic, Randy H. Katz, Jonathan Bachrach, Krste Asanovic:
FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud. ISCA 2018: 29-42 - 2017
- [c3]Jack Koenig, David Biancolin, Jonathan Bachrach, Krste Asanovic:
A Hardware Accelerator for Computing an Exact Dot Product. ARITH 2017: 114-121 - 2016
- [j1]Alex Rodionov, David Biancolin, Jonathan Rose:
Fine-Grained Interconnect Synthesis. ACM Trans. Reconfigurable Technol. Syst. 9(4): 31:1-31:22 (2016) - [c2]Jonathan Bachrach, David Biancolin, Austin Buchan, Duncan W. Haldane, Richard Lin:
JITPCB. IROS 2016: 2230-2236 - 2015
- [c1]Alex Rodionov, David Biancolin, Jonathan Rose:
Fine-Grained Interconnect Synthesis. FPGA 2015: 46-55
Coauthor Index
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