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Surajeet Ghosh
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2020 – today
- 2024
- [j7]Ardhendu Sarkar, Surajeet Ghosh
:
Power-Efficient Pipelined Multiprocessor Architecture With Parallel Trace-Back Mechanism for Multiple Pairwise Sequence Alignment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(8): 2365-2378 (2024) - 2023
- [j6]Surajeet Ghosh
, Sanchita Saha Ray
:
${O(N)}$O(N) Memory-Free Hardware Architecture for Burrows-Wheeler Transform. IEEE Trans. Computers 72(7): 2080-2093 (2023) - [j5]Sanchita Saha Ray
, Surajeet Ghosh
:
k-Degree Parallel Comparison-Free Hardware Sorter for Complete Sorting. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(5): 1438-1449 (2023) - 2022
- [j4]Sanchita Saha Ray
, Surajeet Ghosh
, Bhaskar Sardar:
Memory Efficient Hash-Based Longest Prefix Matching Architecture With Zero False +ve and Nearly Zero False -ve Rate for IP Processing. IEEE Trans. Computers 71(6): 1261-1275 (2022) - [j3]Sanchita Saha Ray
, Dulal Adak, Surajeet Ghosh
:
Worst Case O(N) Comparison-Free Hardware Sorting Engine. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(10): 3332-3345 (2022) - [c5]Surajeet Ghosh, Anirban Chand:
CB-RPL: Coordinator-Based RPL for Energy Efficient Routing Mechanism. ANTS 2022: 231-236 - 2020
- [j2]Ardhendu Sarkar
, Som Banerjee, Surajeet Ghosh
:
An Energy-Efficient Pipelined-Multiprocessor Architecture for Biological Sequence Alignment. IEEE Trans. Very Large Scale Integr. Syst. 28(12): 2598-2611 (2020)
2010 – 2019
- 2019
- [c4]Surajeet Ghosh, Shaon Dasgupta, Sanchita Saha Ray:
A Comparison-free Hardware Sorting Engine. ISVLSI 2019: 586-591 - [c3]Ardhendu Sarkar, Kinjal Ray, Debaroti Chowdhury, Kishan Sahu, Solanki Kundu, Surajeet Ghosh:
Time and Space Efficient Optimal Pairwise Sequence Alignment using GPU. TENCON 2019: 423-428 - 2018
- [c2]Sanchita Saha Ray, Sonal Singh, Chandrayan Sengupta, Surajeet Ghosh, Bhaskar Sardar:
A Fine-grained Integrated IP Lookup Engine for Multigigabit IP Processing. ANTS 2018: 1-6 - 2016
- [j1]Sanchita Saha Ray, Surajeet Ghosh
, Bhaskar Sardar:
An SRAM-based novel hardware architecture for longest prefix matching for IP route lookup. Photonic Netw. Commun. 32(3): 359-371 (2016) - 2015
- [c1]Sanchita Saha Ray, Surajeet Ghosh, Bhaskar Sardar:
SRAM based longest prefix matching approach for multigigabit IP processing. IEEE ANTS 2015: 1-6
Coauthor Index
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