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ORCIDJeferson Santiago da Silva
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2020 – today
- 2021
[c8]Thomas Luinaud
, Jeferson Santiago da Silva, J. M. Pierre Langlois, Yvon Savaria:
Design Principles for Packet Deparsers on FPGAs. FPGA 2021: 280-286- [i6]Thomas Luinaud, Jeferson Santiago da Silva, J. M. Pierre Langlois, Yvon Savaria:
Design Principles for Packet Deparsers on FPGAs. CoRR abs/2103.07750 (2021) - 2020
- [c7]Thomas Luinaud, Thibaut Stimpfling, Jeferson Santiago da Silva, Yvon Savaria, J. M. Pierre Langlois:
Unleashing the Power of FPGAs as Programmable Switches. FPGA 2020: 311 - [c6]Thomas Luinaud, Thibaut Stimpfling, Jeferson Santiago da Silva, Yvon Savaria, J. M. Pierre Langlois:
Bridging the Gap: FPGAs as Programmable Switches. HPSR 2020: 1-7 - [i5]Thomas Luinaud, Thibaut Stimpfling, Jeferson Santiago da Silva, Yvon Savaria, J. M. Pierre Langlois:
Bridging the Gap: FPGAs as Programmable Switches. CoRR abs/2004.07733 (2020)
2010 – 2019
- 2019
- [c5]Jeferson Santiago da Silva, François-Raymond Boyer, J. M. Pierre Langlois:
Module-per-Object: A Human-Driven Methodology for C++-Based High-Level Synthesis Design. FCCM 2019: 218-226 - [i4]Jeferson Santiago da Silva, François-Raymond Boyer, J. M. Pierre Langlois:
Module-per-Object: a Human-Driven Methodology for C++-based High-Level Synthesis Design. CoRR abs/1903.06693 (2019) - 2018
- [c4]Jeferson Santiago da Silva, François-Raymond Boyer, J. M. Pierre Langlois:
P4-Compatible High-Level Synthesis of Low Latency 100 Gb/s Streaming Packet Parsers in FPGAs. FPGA 2018: 147-152 - [c3]Jeferson Santiago da Silva, Thibaut Stimpfling, Thomas Luinaud, Bachir Fradj, Bochra Boughzala:
One for All, All for One: A Heterogeneous Data Plane for Flexible P4 Processing. ICNP 2018: 440-441 - [c2]Jeferson Santiago da Silva, François-Raymond Boyer, Laurent-Olivier Chiquette, J. M. Pierre Langlois:
Extern Objects in P4: an ROHC Header Compression Scheme Case Study. NetSoft 2018: 517-522 - [i3]Jeferson Santiago da Silva, Thibaut Stimpfling, Thomas Luinaud, Bachir Fradj, Bochra Boughzala:
One for All, All for One: A Heterogeneous Data Plane for Flexible P4 Processing. CoRR abs/1807.08870 (2018) - 2017
- [i2]Jeferson Santiago da Silva, François-Raymond Boyer, J. M. Pierre Langlois:
P4-compatible High-level Synthesis of Low Latency 100 Gb/s Streaming Packet Parsers in FPGAs. CoRR abs/1711.06613 (2017) - 2016
- [i1]Jeferson Santiago da Silva, François-Raymond Boyer, Laurent-Olivier Chiquette, J. M. Pierre Langlois:
Extern Objects in P4: an ROHC Compression Case Study. CoRR abs/1611.05943 (2016) - 2015
- [c1]Jeferson Santiago da Silva, Sergio Bampi:
Area-oriented iterative method for Design Space Exploration with High-Level Synthesis. LASCAS 2015: 1-4
Coauthor Index
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