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2020 – today
- 2024
[c10]Armand Behroozi
, Yuxiang Chen, Vlad Fruchter, Lavanya Subramanian, Sriseshan Srikanth, Scott A. Mahlke:
SlimSLAM: An Adaptive Runtime for Visual-Inertial Simultaneous Localization and Mapping. ASPLOS (3) 2024: 900-915- 2022
- [j4]Bobin Deng, Sriseshan Srikanth, Anirudh Jain, Thomas M. Conte, Erik DeBenedictis, Jeanine E. Cook:
Scalable Energy-Efficient Microarchitectures With Computational Error Tolerance Via Redundant Residue Number Systems. IEEE Trans. Computers 71(3): 613-627 (2022) - 2021
- [j3]Sriseshan Srikanth, Anirudh Jain, Thomas M. Conte, Erik P. DeBenedictis, Jeanine E. Cook:
SortCache: Intelligent Cache Management for Accelerating Sparse Data Workloads. ACM Trans. Archit. Code Optim. 18(4): 56:1-56:24 (2021) - 2020
- [b1]Sriseshan Srikanth:
Energy efficient architectures for irregular data streams. Georgia Institute of Technology, Atlanta, GA, USA, 2020 - [j2]Sriseshan Srikanth, Anirudh Jain, Joseph M. Lennon, Thomas M. Conte, Erik DeBenedictis, Jeanine E. Cook:
MetaStrider: Architectures for Scalable Memory-centric Reduction of Sparse Data Streams. ACM Trans. Archit. Code Optim. 16(4): 35:1-35:26 (2020) - [c9]Tong Zhou, Jun Shirako, Anirudh Jain, Sriseshan Srikanth, Thomas M. Conte, Richard W. Vuduc, Vivek Sarkar:
Intrepydd: performance, productivity, and portability for data science application kernels. Onward! 2020: 65-83
2010 – 2019
- 2019
- [c8]Jeffrey S. Young, E. Jason Riedy, Thomas M. Conte, Vivek Sarkar, Prasanth Chatarasi, Sriseshan Srikanth:
Experimental Insights from the Rogues Gallery. ICRC 2019: 80-87 - 2018
- [j1]Bobin Deng, Sriseshan Srikanth, Eric R. Hein, Thomas M. Conte, Erik DeBenedictis, Jeanine E. Cook, Michael P. Frank:
Extending Moore's Law via Computationally Error-Tolerant Computing. ACM Trans. Archit. Code Optim. 15(1): 8:1-8:27 (2018) - [c7]Sriseshan Srikanth, Paul G. Rabbat, Eric R. Hein, Bobin Deng, Thomas M. Conte, Erik DeBenedictis, Jeanine E. Cook, Michael P. Frank:
Memory System Design for Ultra Low Power, Computationally Error Resilient Processor Microarchitectures. HPCA 2018: 696-709 - [c6]Anirudh Jain, Sriseshan Srikanth, Erik P. DeBenedictis, Tushar Krishna:
Merge Network for a Non-Von Neumann Accumulate Accelerator in a 3D Chip. ICRC 2018: 1-11 - [c5]Sriseshan Srikanth, Lavanya Subramanian, Sreenivas Subramoney, Thomas M. Conte, Hong Wang:
Tackling memory access latency through DRAM row management. MEMSYS 2018: 137-147 - 2017
- [c4]Erik P. DeBenedictis, Jeanine E. Cook, Sriseshan Srikanth, Thomas M. Conte:
Superstrider associative array architecture: Approved for unlimited unclassified release: SAND2017-7089 C. HPEC 2017: 1-7 - [c3]Sriseshan Srikanth, Thomas M. Conte, Erik P. DeBenedictis, Jeanine E. Cook:
The Superstrider Architecture: Integrating Logic and Memory Towards Non-Von Neumann Computing. ICRC 2017: 1-8 - 2016
- [c2]Sapan Agarwal, Jeanine E. Cook, Erik DeBenedictis, Michael P. Frank, Gert Cauwenberghs, Sriseshan Srikanth, Bobin Deng, Eric R. Hein, Paul G. Rabbat, Thomas M. Conte:
Energy efficiency limits of logic and memory. ICRC 2016: 1-8 - [c1]Bobin Deng, Sriseshan Srikanth, Eric R. Hein, Paul G. Rabbat, Thomas M. Conte, Erik DeBenedictis, Jeanine E. Cook:
Computationally-redundant energy-efficient processing for y'all (CREEPY). ICRC 2016: 1-8 - [i1]Sriseshan Srikanth, Bobin Deng, Thomas M. Conte:
A Brief Survey of Non-Residue Based Computational Error Correction. CoRR abs/1611.03099 (2016)
Coauthor Index
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