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ORCIDAnkit Jindal
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2010 – 2019
- 2018
[c9]Ankit Jindal, Binod Kumar, Nitish Jindal, Masahiro Fujita, Virendra Singh:
Silicon Debug with Maximally Expanded Internal Observability Using Nearest Neighbor Algorithm. ISVLSI 2018: 46-51- [c8]Ankit Jindal, Binod Kumar, Kanad Basu, Masahiro Fujita:
ELURA: A Methodology for Post-Silicon Gate-Level Error Localization Using Regression Analysis. VLSID 2018: 410-415 - 2017
- [c7]Binod Kumar, Ankit Jindal, Masahiro Fujita, Virendra Singh:
Combining Restorability and Error Detection Ability for Effective Trace Signal Selection. ACM Great Lakes Symposium on VLSI 2017: 191-196 - [c6]Binod Kumar, Ankit Jindal, Jaynarayan T. Tudu
, Brajesh Pandey, Virendra Singh:
Revisiting random access scan for effective enhancement of post-silicon observability. IOLTS 2017: 132-137 - [c5]Binod Kumar, Ankit Jindal, Masahiro Fujita, Virendra Singh:
Post-silicon observability enhancement with topology based trace signal selection. LATS 2017: 1-6 - [c4]Binod Kumar, Kanad Basu, Ankit Jindal, Brajesh Pandey, Masahiro Fujita:
A Formal Perspective on Effective Post-silicon Debug and Trace Signal Selection. VDAT 2017: 753-766 - [c3]Binod Kumar, Kanad Basu, Ankit Jindal, Masahiro Fujita, Virendra Singh:
Improving post-silicon error detection with topological selection of trace signals. VLSI-SoC 2017: 1-6 - [c2]Binod Kumar, Ankit Jindal, Virendra Singh, Masahiro Fujita:
A Methodology for Trace Signal Selection to Improve Error Detection in Post-Silicon Validation. VLSID 2017: 147-152 - 2016
- [c1]Binod Kumar, Ankit Jindal, Virendra Singh:
A trace signal selection algorithm for improved post-silicon debug. EWDTS 2016: 1-4
Coauthor Index
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