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Xiumin Xu
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2010 – 2019
- 2018
- [c3]Gaoliang Ma, Huaguo Liang, Liang Yao, Zhengfeng Huang, Maoxiang Yi, Xiumin Xu, Kai Zhou:
A Low-Cost High-Efficiency True Random Number Generator on FPGAs. ATS 2018: 54-58 - [c2]Xiumin Xu, Huaguo Liang, Kai Zhou, Gaoliang Ma, Zhengfeng Huang, Maoxiang Yi, Tianming Ni, Yingchun Lu:
An All-Digital and Jitter-Quantizing True Random Number Generator in SRAM-Based FPGAs. ATS 2018: 59-62 - [c1]Kai Zhou, Huaguo Liang, Yue Jiang, Zhengfeng Huang, Maoxiang Yi, Xiumin Xu, Yao Yao:
A High Reliability FPGA Chip Identification Generator Based on PDLs. ATS 2018: 63-67 - 2017
- [j6]Xiumin Xu, Huaguo Liang, Zhengfeng Huang, Cuiyun Jiang, Yingchun Lu, Aibin Yan, Tianming Ni, Maoxiang Yi:
A single event transient detector in SRAM-based FPGAs. IEICE Electron. Express 14(12): 20170210 (2017) - [j5]Xiumin Xu, Huaguo Liang, Zhengfeng Huang, Cuiyun Jiang, Yiming Ouyang, Xiangsheng Fang, Tianming Ni, Maoxiang Yi:
A highly reliable butterfly PUF in SRAM-based FPGAs. IEICE Electron. Express 14(14): 20170551 (2017) - [j4]Tianming Ni, Mu Nie, Huaguo Liang, Jingchang Bian, Xiumin Xu, Xiangsheng Fang, Zhengfeng Huang, Xiaoqing Wen:
Vernier ring based pre-bond through silicon vias test in 3D ICs. IEICE Electron. Express 14(18): 20170590 (2017) - [j3]Huaguo Liang, Xin Li, Zhengfeng Huang, Aibin Yan, Xiumin Xu:
Highly Robust Double Node Upset Resilient Hardened Latch Design. IEICE Trans. Electron. 100-C(5): 496-503 (2017) - [j2]Tianming Ni, Huaguo Liang, Mu Nie, Xiumin Xu, Aibin Yan, Zhengfeng Huang:
A Region-Based Through-Silicon via Repair Method for Clustered Faults. IEICE Trans. Electron. 100-C(12): 1108-1117 (2017) - [j1]Aibin Yan
, Zhengfeng Huang, Maoxiang Yi
, Xiumin Xu, Yiming Ouyang, Huaguo Liang:
Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology. IEEE Trans. Very Large Scale Integr. Syst. 25(6): 1978-1982 (2017)
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last updated on 2024-04-25 05:43 CEST by the dblp team
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