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Chen-Shang Lin

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1990 – 1999

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1997
[j4]
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Kuan-Jen Lin, Chi-Wen Kuo, Chen-Shang Lin:
Synthesis of Hazard-Free Asynchronous Circuits Based on Characteristic Graph. IEEE Trans. Computers 46(11): 1246-1263 (1997)
1996
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Chen-Pin Kung, Chen-Shang Lin:
Parallel sequence fault simulation for synchronous sequential circuits. J. Electron. Test. 9(3): 267-277 (1996)
1995
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Jau-Shien Chang, Chen-Shang Lin:
Test set compaction for combinational circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(11): 1370-1378 (1995)
[c9]
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Chen-Pin Kung, Chun-Jieh Huang, Chen-Shang Lin:
Fast fault simulation for BIST applications. Asian Test Symposium 1995: 93-99
1994
[c8]
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Kuan-Jen Lin, Jih-Wen Kuo, Chen-Shang Lin:
Direct Synthesis of Hazard-Free Asynchronous Circuits from STGs Based on Lock Relation and BG-Decomposition Approach. EDAC-ETC-EUROASIC 1994: 178-183
[c7]
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Chen-Pin Kung, Chen-Shang Lin:
HyHOPE: a fast fault simulator with efficient simulation of hypertrophic faults. ICCAD 1994: 714-718
[c6]
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Jau-Shien Chang, Chen-Shang Lin:
A Test-Clock Reduction Method for Scan-Designed Circuits. ITC 1994: 331-339
1992
[j1]
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Heh-Tyan Liaw, Chen-Shang Lin:
On the OBDD-Representation of General Boolean Functions. IEEE Trans. Computers 41(6): 661-664 (1992)
[c5]
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Kuan-Jen Lin, Chen-Shang Lin:
On the verification of state-coding in STGs. ICCAD 1992: 118-122
1991
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Kuan-Jen Lin, Chen-Shang Lin:
Automatic Synthesis of Asynchronous Circuits. DAC 1991: 296-301
1990
[c3]
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Heh-Tyan Liaw, Jia-Horng Tsaih, Chen-Shang Lin:
Efficient Automatic Diagnosis of Digital Circuits. ICCAD 1990: 464-467

1980 – 1989

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1989
[c2]
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Heh-Tyan Liaw, K.-T. Tran, Chen-Shang Lin:
VVDS: A Verification/Diagnosis System for VHDL. DAC 1989: 435-440
1988
[c1]
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Chen-Shang Lin, Hong-Fa Ho:
Automatic Functional Test Program Generation for Microprocessors. DAC 1988: 605-608

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