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ORCIDAtsushi Hasegawa
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2020 – today
- 2022
[j8]Zihang Li
, Atsushi Hasegawa, Takuya Azumi:
Autoware_Perf: A tracing and performance analysis framework for ROS 2 applications. J. Syst. Archit. 123: 102341 (2022)- [c13]Takahisa Kuboichi, Atsushi Hasegawa, Bo Peng, Keita Miura, Kenji Funaoka, Shinpei Kato, Takuya Azumi:
CARET: Chain-Aware ROS 2 Evaluation Tool. EUC 2022: 1-8 - [c12]Bo Peng, Atsushi Hasegawa, Takuya Azumi:
Scheduling Performance Evaluation Framework for ROS 2 Applications. HPCC/DSS/SmartCity/DependSys 2022: 2031-2038 - 2021
- [c11]Jun Iio, Atsushi Hasegawa, Shigeyoshi Iizuka, Seiji Hayakawa, Hiroshi Tsujioka:
Ethics in Human-Centered Design. HCI (1) 2021: 161-170
2010 – 2019
- 2010
- [j7]Makoto Saen, Kenichi Osada, Yasuyuki Okuma, Kiichi Niitsu, Yasuhisa Shimazaki, Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga, Itaru Nonomura, Naohiko Irie, Toshihiro Hattori, Atsushi Hasegawa, Tadahiro Kuroda:
3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link. IEEE J. Solid State Circuits 45(4): 856-862 (2010) - [c10]Yoichi Yuyama, Masayuki Ito, Yoshikazu Kiyoshige, Yusuke Nitta, Shigezumi Matsui, Osamu Nishii, Atsushi Hasegawa, Makoto Ishikawa, Tetsuya Yamada, Junichi Miyakoshi, Koichi Terada, Tohru Nojiri, Masashi Satoh, Hiroyuki Mizuno, Kunio Uchiyama, Yasutaka Wada, Keiji Kimura, Hironori Kasahara, Hideo Maejima:
A 45nm 37.3GOPS/W heterogeneous multi-core SoC. ISSCC 2010: 100-101
2000 – 2009
- 2009
- [c9]Atsushi Hasegawa:
Site-it!: An Information Architecture Prototyping Tool. HCI (10) 2009: 707-711 - [c8]Kiichi Niitsu, Yasuhisa Shimazaki, Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga, Itaru Nonomura, Makoto Saen, Shigenobu Komatsu, Kenichi Osada, Naohiko Irie, Toshihiro Hattori, Atsushi Hasegawa, Tadahiro Kuroda:
An inductive-coupling link for 3D integration of a 90nm CMOS processor and a 65nm CMOS SRAM. ISSCC 2009: 480-481 - 2008
- [c7]Masayuki Ito, Toshihiro Hattori, Yutaka Yoshida, Kiyoshi Hayase, Tomoichi Hayashi, Osamu Nishii, Yoshihiko Yasu, Atsushi Hasegawa, Masashi Takada, Hiroyuki Mizuno, Kunio Uchiyama, Toshihiko Odaka, Jun Shirako, Masayoshi Mase, Keiji Kimura, Hironori Kasahara:
An 8640 MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs by An Automatic Parallelizing Compiler. ISSCC 2008: 90-91 - 2007
- [j6]Kazutami Arimoto, Toshihiro Hattori, Hidehiro Takata, Atsushi Hasegawa, Toru Shimizu:
Continuous Design Efforts for Ubiquitous Network Era under the Physical Limitation of Advanced CMOS. IEICE Trans. Electron. 90-C(4): 657-665 (2007) - [c6]Atsushi Hasegawa:
Recent Trend in Industry and Expectation to DA Research. ATVA 2007: 15-16 - [c5]Yutaka Yoshida, Tatsuya Kamei, Kiyoshi Hayase, Shinichi Shibahara, Osamu Nishii, Toshihiro Hattori, Atsushi Hasegawa, Masashi Takada, Naohiko Irie, Kunio Uchiyama, Toshihiko Odaka, Kiwamu Takada, Keiji Kimura, Hironori Kasahara:
A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption. ISSCC 2007: 100-590 - 2005
- [j5]Jungpil Shin, Kazunori Suzuki, Atsushi Hasegawa:
Handwritten Chinese Character Font Generation Based on Stroke Correspondence. Int. J. Comput. Process. Orient. Lang. 18(3): 211-226 (2005) - 2003
- [c4]Tatsuo Nakajima, Atsushi Hasegawa, Tomoyoshi Akutagawa, Akihiro Ibe, Kouji Yamamoto:
Making Existing Interactive Applications Context-Aware. Euro-Par 2003: 1082-1090 - [c3]John A. Vaccaro, Yasuyoshi Mitsumori, Stephen M. Barnett, Erika Andersson, Atsushi Hasegawa, Masahiro Takeoka, Masahide Sasaki:
Quantum Data Compression (Invited Talk). SAGA 2003: 98-107 - 2002
- [c2]Tatsuo Nakajima, Atsushi Hasegawa:
Universal Interaction with Networked Home Appliances. ICDCS 2002: 451-452 - 2001
- [j4]Mitsuhisa Sato, Hiroshi Harada, Atsushi Hasegawa:
Cluster-enabled OpenMP: An OpenMP compiler for the SCASH software distributed shared memory system. Sci. Program. 9(2-3): 123-130 (2001) - [c1]Atsushi Hasegawa, Tatsuo Nakajima:
A User Interface System for Home Appliances with Virtual Network Computing. ICDCS Workshops 2001: 229-234 - 2000
- [j3]Prasenjit Biswas, Atsushi Hasegawa, Srinivas Mandaville, Mark Debbage, Andy Sturges, Fumio Arakawa, Yasuhiko Saito, Kunio Uchiyama:
SH-5: The 64-Bit SuperH Architecture. IEEE Micro 20(4): 28-39 (2000)
1990 – 1999
- 1995
- [j2]Atsushi Hasegawa, Ikuya Kawasaki, Kouji Yamada, Shinichi Yoshioka, Shumpei Kawasaki, Prasenjit Biswas:
SH3: high code density, low power. IEEE Micro 15(6): 11-19 (1995) - 1994
- [j1]Thomas R. Gross, Susan Hinrichs, David R. O'Hallaron, Thomas Stricker, Atsushi Hasegawa:
Communication Styles for Parallel Systems. Computer 27(12): 34-44 (1994)
Coauthor Index
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