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ORCIDRussell Tessier
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- affiliation: University of Massachusetts Amherst, USA
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2020 – today
- 2021
[j42]Shayan Moini
, Shanquan Tian, Daniel E. Holcomb, Jakub Szefer, Russell Tessier:
Power Side-Channel Attacks on BNN Accelerators in Remote FPGAs. IEEE J. Emerg. Sel. Topics Circuits Syst. 11(2): 357-370 (2021)- [j41]Florian Stolz, Nils Albartus, Julian Speith, Simon Klix, Clemens Nasenberg, Aiden Gula, Marc Fyrbiak, Christof Paar, Tim Güneysu, Russell Tessier:
LifeLine for FPGA Protection: Obfuscated Cryptography for Real-World Security. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2021(4): 412-446 (2021) - [c86]Shayan Moini, Shanquan Tian, Daniel E. Holcomb, Jakub Szefer, Russell Tessier:
Remote Power Side-Channel Attacks on BNN Accelerators in FPGAs. DATE 2021: 1639-1644 - [c85]Shanquan Tian, Shayan Moini, Adam Wolnikowski, Daniel E. Holcomb, Russell Tessier, Jakub Szefer:
Remote Power Attacks on the Versatile Tensor Accelerator in Multi-Tenant FPGAs. FCCM 2021: 242-246 - [c84]Nils Albartus, Clemens Nasenberg, Florian Stolz, Marc Fyrbiak, Christof Paar, Russell Tessier:
On the Design and Misuse of Microcoded (Embedded) Processors - A Cautionary Note. USENIX Security Symposium 2021: 267-284 - [i6]Nils Albartus, Clemens Nasenberg, Florian Stolz, Marc Fyrbiak, Christof Paar, Russell Tessier:
On the Design and Misuse of Microcoded (Embedded) Processors - A Cautionary Note. IACR Cryptol. ePrint Arch. 2021: 663 (2021) - [i5]Florian Stolz, Nils Albartus, Julian Speith, Simon Klix, Clemens Nasenberg, Aiden Gula, Marc Fyrbiak, Christof Paar, Tim Güneysu, Russell Tessier:
LifeLine for FPGA Protection: Obfuscated Cryptography for Real-World Security. IACR Cryptol. ePrint Arch. 2021: 1277 (2021) - 2020
- [j40]Xuzhi Zhang, Xiaozhe Shao, George Provelengios, Naveen Kumar Dumpala, Lixin Gao, Russell Tessier:
CoNFV: A Heterogeneous Platform for Scalable Network Function Virtualization. ACM Trans. Reconfigurable Technol. Syst. 14(1): 1:1-1:29 (2020) - [j39]George Provelengios, Daniel E. Holcomb, Russell Tessier:
Power Distribution Attacks in Multitenant FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 28(12): 2685-2698 (2020) - [c83]George Provelengios, Daniel E. Holcomb, Russell Tessier:
Power Wasting Circuits for Cloud FPGA Attacks. FPL 2020: 231-235 - [c82]Xiang Li, Peter Stanwicks, George Provelengios, Russell Tessier, Daniel E. Holcomb:
Jitter-based Adaptive True Random Number Generation for FPGAs in the Cloud. FPT 2020: 112-119 - [c81]Xuzhi Zhang, Russell Tessier:
Service Chaining for Heterogeneous Middleboxes. FPT 2020: 263-267 - [c80]Shayan Moini, Xiang Li, Peter Stanwicks, George Provelengios, Wayne P. Burleson, Russell Tessier, Daniel E. Holcomb:
Understanding and Comparing the Capabilities of On-Chip Voltage Sensors against Remote Power Attacks on FPGAs. MWSCAS 2020: 941-944 - [c79]Xuzhi Zhang, Narendra Prabhu, Russell Tessier:
NestedNet: A Container-based Prototyping Tool for Hierarchical Software Defined Networks. RSP 2020: 1-7 - [i4]Shayan Moini, Shanquan Tian, Jakub Szefer, Daniel E. Holcomb, Russell Tessier:
Remote Power Side-Channel Attacks on CNN Accelerators in FPGAs. CoRR abs/2011.07603 (2020)
2010 – 2019
- 2019
- [j38]Marc Fyrbiak, Sebastian Wallat, Pawel Swierczynski, Max Hoffmann, Sebastian Hoppach, Matthias Wilhelm, Tobias Weidlich, Russell Tessier, Christof Paar:
HAL - The Missing Piece of the Puzzle for Hardware Reverse Engineering, Trojan Detection and Insertion. IEEE Trans. Dependable Secur. Comput. 16(3): 498-510 (2019) - [j37]Naveen Kumar Dumpala, Shivukumar B. Patil, Daniel E. Holcomb, Russell Tessier:
Loop Unrolling for Energy Efficiency in Low-Cost Field-Programmable Gate Arrays. ACM Trans. Reconfigurable Technol. Syst. 11(4): 26:1-26:23 (2019) - [j36]Christophe Bobda, Russell Tessier, Ken Eguro, Ryan Kastner:
Introduction to the Special Section on Security in FPGA-accelerated Cloud and Datacenters. ACM Trans. Reconfigurable Technol. Syst. 12(3) (2019) - [j35]Mohammad A. Usmani, Shahrzad Keshavarz, Eric Matthews, Lesley Shannon, Russell Tessier, Daniel E. Holcomb:
Efficient PUF-Based Key Generation in FPGAs Using Per-Device Configuration. IEEE Trans. Very Large Scale Integr. Syst. 27(2): 364-375 (2019) - [c78]George Provelengios, Chethan Ramesh, Shivukumar B. Patil, Ken Eguro, Russell Tessier, Daniel E. Holcomb:
Characterization of Long Wire Data Leakage in Deep Submicron FPGAs. FPGA 2019: 292-297 - [c77]George Provelengios, Daniel E. Holcomb, Russell Tessier:
Characterizing Power Distribution Attacks in Multi-User FPGA Environments. FPL 2019: 194-201 - [c76]Lijuan Xia, Ahmed Soltan, Xuzhi Zhang, Andrew Jackson, Russell Tessier, Patrick Degenaar:
Closed-Loop Proportion-Derivative Control of Suppressing Seizures in a Neural Mass Model. ISCAS 2019: 1-5 - [i3]Marc Fyrbiak, Sebastian Wallat, Jonathan Déchelotte, Nils Albartus, Sinan Böcker, Russell Tessier, Christof Paar:
On the Difficulty of FSM-based Hardware Obfuscation. IACR Cryptol. ePrint Arch. 2019: 1163 (2019) - 2018
- [j34]Marc Fyrbiak, Simon Rokicki, Nicolai Bissantz, Russell Tessier, Christof Paar:
Hybrid Obfuscation to Protect Against Disclosure Attacks on Embedded Microprocessors. IEEE Trans. Computers 67(3): 307-321 (2018) - [j33]Marc Fyrbiak, Sebastian Wallat, Jonathan Déchelotte, Nils Albartus, Sinan Böcker, Russell Tessier, Christof Paar:
On the Difficulty of FSM-based Hardware Obfuscation. IACR Trans. Cryptogr. Hardw. Embed. Syst. 2018(3): 293-330 (2018) - [c75]Shivukumar B. Patil, Tianqi Liu, Russell Tessier:
A Bandwidth-Optimized Routing Algorithm for Hybrid FPGA Networks-on-Chip. FCCM 2018: 25-28 - [c74]Chethan Ramesh, Shivukumar B. Patil, Siva Nishok Dhanuskodi, George Provelengios, Sébastien Pillement, Daniel E. Holcomb, Russell Tessier:
FPGA Side Channel Attacks without Physical Access. FCCM 2018: 45-52 - [c73]Jonathan Déchelotte, Russell Tessier, Dominique Dallet, Jérémie Crenne:
Lynq: A Lightweight Software Layer for Rapid SoC FPGA Prototyping. FPL 2018: 372-375 - [c72]George Provelengios, Arman Pouraghily, Russell Tessier, Tilman Wolf:
A Hardware Monitor to Protect Linux System Calls. ISVLSI 2018: 551-556 - 2017
- [j32]Vincent Migliore, Cédric Seguin, Maria Mendez Real, Vianney Lapotre, Arnaud Tisserand, Caroline Fontaine, Guy Gogniat, Russell Tessier:
A High-Speed Accelerator for Homomorphic Encryption using the Karatsuba Algorithm. ACM Trans. Embed. Comput. Syst. 16(5s): 138:1-138:17 (2017) - [c71]Arman Pouraghily, Tilman Wolf, Russell Tessier:
Hardware support for embedded operating system security. ASAP 2017: 61-66 - [c70]Naveen Kumar Dumpala, Shivukumar B. Patil, Daniel E. Holcomb, Russell Tessier:
Energy Efficient Loop Unrolling for Low-Cost FPGAs. FCCM 2017: 117-120 - [c69]Xuzhi Zhang, Xiaozhe Shao, George Provelengios, Naveen Kumar Dumpala, Lixin Gao, Russell Tessier:
Scalable Network Function Virtualization for Heterogeneous Middleboxes. FCCM 2017: 219-226 - [i2]Marc Fyrbiak, Sebastian Wallat, Pawel Swierczynski, Max Hoffmann, Sebastian Hoppach, Matthias Wilhelm, Tobias Weidlich, Russell Tessier, Christof Paar:
HAL- The Missing Piece of the Puzzle for Hardware Reverse Engineering, Trojan Detection and Insertion. IACR Cryptol. ePrint Arch. 2017: 783 (2017) - 2016
- [j31]Kekai Hu, Harikrishnan Kumarapillai Chandrikakutty, Zachary Goodman, Russell Tessier, Tilman Wolf:
Dynamic Hardware Monitors for Network Processor Protection. IEEE Trans. Computers 65(3): 860-872 (2016) - [c68]Christophe Huriaux, Olivier Sentieys, Russell Tessier:
Effects of I/O routing through column interfaces in embedded FPGA fabrics. FPL 2016: 1-9 - [c67]Shrikant Vyas, Naveen Kumar Dumpala, Russell Tessier, Daniel E. Holcomb:
Improving the efficiency of PUF-based key generation in FPGAs using variation-aware placement. FPL 2016: 1-4 - [c66]Tianqi Liu, Naveen Kumar Dumpala, Russell Tessier:
Hybrid hard NoCs for efficient FPGA communication. FPT 2016: 157-164 - [i1]Kevin Andryc, Tedy Thomas, Russell Tessier:
Soft GPGPUs for Embedded FPGAs: An Architectural Evaluation. CoRR abs/1606.06454 (2016) - 2015
- [j30]Russell Tessier, Kenneth L. Pocek, André DeHon:
Reconfigurable Computing Architectures. Proc. IEEE 103(3): 332-354 (2015) - [j29]Tilman Wolf, Harikrishnan Kumarapillai Chandrikakutty, Kekai Hu, Deepak Unnikrishnan, Russell Tessier:
Securing Network Processors with High-Performance Hardware Monitors. IEEE Trans. Dependable Secur. Comput. 12(6): 652-664 (2015) - [c65]Tedy Thomas, Arman Pouraghily, Kekai Hu, Russell Tessier, Tilman Wolf:
Multi-task support for security-enabled embedded processors. ASAP 2015: 136-143 - [c64]Meha Kainth, Lekshmi Krishnan, Chaitra Narayana, Sandesh Gubbi Virupaksha, Russell Tessier:
Hardware-assisted code obfuscation for FPGA soft microprocessors. DATE 2015: 127-132 - [c63]Pawel Swierczynski, Marc Fyrbiak, Christof Paar, Christophe Huriaux, Russell Tessier:
Protecting against Cryptographic Trojans in FPGAs. FCCM 2015: 151-154 - [c62]Xiaobin Liu, Tedy Thomas, Alan Boguslawski, Russell Tessier:
Adaptive MRAM-based CGRAs. FPL 2015: 1-4 - [c61]Shiting (Justin) Lu, Russell Tessier, Wayne P. Burleson:
Reinforcement Learning for Thermal-aware Many-core Task Allocation. ACM Great Lakes Symposium on VLSI 2015: 379-384 - 2014
- [j28]Shiting (Justin) Lu, Russell Tessier, Wayne P. Burleson:
Dynamic On-Chip Thermal Sensor Calibration Using Performance Counters. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(6): 853-866 (2014) - [c60]Kekai Hu, Tilman Wolf, Thiago Teixeira, Russell Tessier:
System-Level Security for Network Processors with Hardware Monitors. DAC 2014: 211:1-211:6 - [c59]Christophe Huriaux, Olivier Sentieys, Russell Tessier:
FPGA Architecture Enhancements to Support Heterogeneous Partially Reconfigurable Regions. FCCM 2014: 30 - [c58]Christophe Huriaux, Olivier Sentieys, Russell Tessier:
FPGA architecture support for heterogeneous, relocatable partial bitstreams. FPL 2014: 1-6 - [c57]Jia Zhao, Shiting (Justin) Lu, Wayne P. Burleson, Russell Tessier:
A Broadcast-Enabled Sensing System for Embedded Multi-core Processors. ISVLSI 2014: 190-195 - 2013
- [j27]Shiting (Justin) Lu, Paul Siqueira, Vishwas Vijayendra, Harikrishnan Chandrikakutty, Russell Tessier:
Real-Time Differential Signal Phase Estimation for Space-Based Systems using FPGAs. IEEE Trans. Aerosp. Electron. Syst. 49(2): 1192-1209 (2013) - [j26]Deepak Unnikrishnan, Ramakrishna Vadlamani, Yong Liao, Jérémie Crenne, Lixin Gao, Russell Tessier:
Reconfigurable Data Planes for Scalable Network Virtualization. IEEE Trans. Computers 62(12): 2476-2488 (2013) - [j25]Jérémie Crenne, Romain Vaslin, Guy Gogniat, Jean-Philippe Diguet, Russell Tessier, Deepak Unnikrishnan:
Configurable memory security in embedded systems. ACM Trans. Embed. Comput. Syst. 12(3): 71:1-71:23 (2013) - [c56]Kekai Hu, Harikrishnan Chandrikakutty, Russell Tessier, Tilman Wolf:
Scalable hardware monitors to protect network processors from data plane attacks. CNS 2013: 314-322 - [c55]Harikrishnan Chandrikakutty, Deepak Unnikrishnan, Russell Tessier, Tilman Wolf:
High-performance hardware monitors to protect network processors from data plane attacks. DAC 2013: 80:1-80:6 - [c54]Jia Zhao, Shiting (Justin) Lu, Wayne P. Burleson, Russell Tessier:
Run-time probabilistic detection of miscalibrated thermal sensors in many-core systems. DATE 2013: 1395-1398 - [c53]Daniel Gomez-Prado, Maciej J. Ciesielski, Russell Tessier:
FPGA latency optimization using system-level transformations and DFG restructuring. DATE 2013: 1553-1558 - [c52]Deepak Unnikrishnan, Sandesh Gubbi Virupaksha, Lekshmi Krishnan, Lixin Gao, Russell Tessier:
Accelerating iterative algorithms with asynchronous accumulative updates on FPGAs. FPT 2013: 66-73 - [c51]Kevin Andryc, Murtaza Merchant, Russell Tessier:
FlexGrip: A soft GPGPU for FPGAs. FPT 2013: 230-237 - [c50]Cory Gorman, Paul Siqueira, Russell Tessier:
An open-source SATA core for Virtex-4 FPGAs. FPT 2013: 454-457 - 2012
- [c49]Jia Zhao, Russell Tessier, Wayne P. Burleson:
Distributed sensor data processing for many-cores. ACM Great Lakes Symposium on VLSI 2012: 159-164 - [c48]Y. Sinan Hanay, Wei Li, Russell Tessier, Tilman Wolf:
Saving energy and improving TCP throughput with rate adaptation in Ethernet. ICC 2012: 1249-1254 - [c47]Shiting (Justin) Lu, Russell Tessier, Wayne P. Burleson:
Collaborative calibration of on-chip thermal sensors using performance counters. ICCAD 2012: 15-22 - 2011
- [j24]Dong Yin, Deepak Unnikrishnan, Yong Liao, Lixin Gao, Russell Tessier:
Customizing virtual networks with partial FPGA reconfiguration. Comput. Commun. Rev. 41(1): 125-132 (2011) - [j23]Tilman Wolf, Russell Tessier, Gayatri Prabhu:
Securing the data path of next-generation router systems. Comput. Commun. 34(4): 598-606 (2011) - [j22]Jia Zhao, Sailaja Madduri, Ramakrishna Vadlamani, Wayne P. Burleson, Russell Tessier:
A Dedicated Monitoring Infrastructure for Multicore Processors. IEEE Trans. Very Large Scale Integr. Syst. 19(6): 1011-1022 (2011) - [c46]Vishwas Vijayendra, Paul Siqueira, Harikrishnan Chandrikakutty, Akilesh Krishnamurthy, Russell Tessier:
Real-time estimates of differential signal phase for spaceborne systems using FPGAs. AHS 2011: 121-128 - [c45]Deepak Unnikrishnan, Shiting (Justin) Lu, Lixin Gao, Russell Tessier:
ReClick - A Modular Dataplane Design Framework for FPGA-Based Network Virtualization. ANCS 2011: 145-155 - [c44]Emmanuel Seguin, Russell Tessier, Eric J. Knapp, Robert W. Jackson:
A Dynamically-Reconfigurable Phased Array Radar Processing System. FPL 2011: 258-263 - [c43]Jérémie Crenne, Pascal Cotret, Guy Gogniat, Russell Tessier, Jean-Philippe Diguet:
Efficient key-dependent message authentication in reconfigurable hardware. FPT 2011: 1-6 - [c42]Ben Bovee, Mohammad Nekoui, Hossein Pishro-Nik, Russell Tessier:
Evaluation of the Universal Geocast Scheme for VANETs. VTC Fall 2011: 1-5 - [e5]Russell Tessier:
2011 International Conference on Field-Programmable Technology, FPT 2011, New Delhi, India, December 12-14, 2011. IEEE 2011, ISBN 978-1-4577-1741-3 [contents] - 2010
- [c41]Ramakrishna Vadlamani, Jia Zhao, Wayne P. Burleson, Russell Tessier:
Multicore soft error rate stabilization using adaptive dual modular redundancy. DATE 2010: 27-32 - [c40]Russell Tessier, Salma Mirza, J. Blair Perot:
Reconfigurable Sparse Matrix-Vector Multiplication on FPGAs. ERSA 2010: 77-83 - [c39]Deepak Unnikrishnan, Ramakrishna Vadlamani, Yong Liao, Abhishek Dwaraki, Jérémie Crenne, Lixin Gao, Russell Tessier:
Scalable network virtualization using FPGAs. FPGA 2010: 219-228 - [c38]Jia Zhao, Basab Datta, Wayne P. Burleson, Russell Tessier:
Thermal-aware voltage droop compensation for multi-core architectures. ACM Great Lakes Symposium on VLSI 2010: 335-340 - [c37]Dong Yin, Deepak Unnikrishnan, Yong Liao, Lixin Gao, Russell Tessier:
Customizing virtual networks with partial FPGA reconfiguration. VISA@SIGCOMM 2010: 57-64 - [e4]Ron Sass, Russell Tessier:
18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2010, Charlotte, North Carolina, USA, 2-4 May 2010. IEEE Computer Society 2010, ISBN 978-0-7695-4056-6 [contents]
2000 – 2009
- 2009
- [j21]Romain Vaslin, Guy Gogniat, Jean-Philippe Diguet, Eduardo Braulio Wanderley Netto, Russell Tessier, Wayne P. Burleson:
A security approach for off-chip memory in embedded microprocessor systems. Microprocess. Microsystems 33(1): 37-45 (2009) - [j20]Weifeng Xu, Russell Tessier:
Tetris-XL: A performance-driven spill reduction technique for embedded VLIW processors. ACM Trans. Archit. Code Optim. 6(3): 11:1-11:40 (2009) - [c36]Sailaja Madduri, Ramakrishna Vadlamani, Wayne P. Burleson, Russell Tessier:
A monitor interconnect and support subsystem for multicore processors. DATE 2009: 761-766 - [c35]Deepak Unnikrishnan, Jia Zhao, Russell Tessier:
Application Specific Customization and Scalability of Soft Multiprocessors. FCCM 2009: 123-130 - [c34]Deming Chen, Russell Tessier, Kaustav Banerjee, Mojy C. Chian, André DeHon, Shinobu Fujita, James Hutchby, Steve Trimberger:
CMOS vs Nano: comrades or rivals? FPGA 2009: 121-122 - [c33]Tilman Wolf, Russell Tessier:
Design of a Secure Router System for Next-Generation Networks. NSS 2009: 52-59 - [c32]Kevin Andryc, Russell Tessier, Patrick Kelly:
An Interactive Approach to Timing Accurate PCI-X Simulation. IEEE International Workshop on Rapid System Prototyping 2009: 181-187 - 2008
- [c31]Romain Vaslin, Guy Gogniat, Jean-Philippe Diguet, Russell Tessier, Deepak Unnikrishnan, Kris Gaj:
Memory security management for reconfigurable embedded systems. FPT 2008: 153-160 - 2007
- [j19]Ian Kuon, Russell Tessier, Jonathan Rose:
FPGA Architecture: Survey and Challenges. Found. Trends Electron. Des. Autom. 2(2): 135-253 (2007) - [j18]Russell Tessier, Vaughn Betz, David Neto, Aaron Egier, Thiagaraja Gopalsamy:
Power-Efficient RAM Mapping Algorithms for FPGA Embedded Memory Blocks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(2): 278-290 (2007) - [c30]Romain Vaslin, Guy Gogniat, Jean-Philippe Diguet, Russell Tessier, Wayne P. Burleson:
High-efficiency protection solution for off-chip memory in embedded systems. ERSA 2007: 117-123 - [c29]Thomas Eisenbarth, Tim Güneysu, Christof Paar, Ahmad-Reza Sadeghi, Marko Wolf, Russell Tessier:
Establishing Chain of Trust in Reconfigurable Hardware. FCCM 2007: 289-290 - [c28]Kevin Oo Tinmaung, David Howland, Russell Tessier:
Power-aware FPGA logic synthesis using binary decision diagrams. FPGA 2007: 148-155 - [c27]Weifeng Xu, Russell Tessier:
Tetris: a new register pressure control technique for VLIW processors. LCTES 2007: 113-122 - [c26]Romain Vaslin, Guy Gogniat, Eduardo Braulio Wanderley Netto, Russell Tessier, Wayne P. Burleson:
Low latency Solution for Confidentiality and Integrity Checking in Embedded Systems with Off-Chip Memory. ReCoSoC 2007: 146-153 - 2006
- [j17]Miriam Leeser, Scott Hauck, Russell Tessier:
Field-Programmable Gate Arrays in Embedded Systems. EURASIP J. Embed. Syst. 2006 (2006) - [j16]Premachandran R. Menon, Weifeng Xu, Russell Tessier:
Design-specific path delay testing in lookup-table-based FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(5): 867-877 (2006) - [c25]Lilian Atieno, Jonathan Allen, Dennis Goeckel, Russell Tessier:
An adaptive Reed-Solomon errors-and-erasures decoder. FPGA 2006: 150-158 - [c24]Russell Tessier, Vaughn Betz, David Neto, Thiagaraja Gopalsamy:
Power-aware RAM mapping for FPGA embedded memory blocks. FPGA 2006: 189-198 - 2005
- [j15]Russell Tessier, Sriram Swaminathan, Ramaswamy Ramaswamy, Dennis Goeckel, Wayne P. Burleson:
A reconfigurable, power-efficient adaptive Viterbi decoder. IEEE Trans. Very Large Scale Integr. Syst. 13(4): 484-488 (2005) - [j14]Russell Tessier, David Jasinski, Atul Maheshwari, Aiyappan Natarajan, Weifeng Xu, Wayne P. Burleson:
An energy-aware active smart card. IEEE Trans. Very Large Scale Integr. Syst. 13(10): 1190-1199 (2005) - [c23]Francesc Junyent, Venkatachalam Chandrasekar, David J. McLaughlin, Stephen J. Frasier, Edin Insanic, Razi Ahmed, Nitin Bharadwaj, Eric J. Knapp, Luko Krnan, Russell Tessier:
Salient features of radar nodes of the first generation NetRad System. IGARSS 2005: 4 - 2004
- [j13]Gordon Farquharson, William N. Junek, Arun Ramanathan, Stephen J. Frasier, Russell Tessier, David J. McLaughlin, Mark A. Sletten, Jakov V. Toporkov:
A pod-based dual-beam SAR. IEEE Geosci. Remote. Sens. Lett. 1(2): 62-65 (2004) - [j12]Atul Maheshwari, Wayne P. Burleson, Russell Tessier:
Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits. IEEE Trans. Very Large Scale Integr. Syst. 12(3): 299-311 (2004) - [j11]Jian Liang, Andrew Laffely, Sriram Srinivasan, Russell Tessier:
An architecture and compiler for scalable on-chip communication. IEEE Trans. Very Large Scale Integr. Syst. 12(7): 711-726 (2004) - [j10]Roger F. Woods, Russell Tessier:
Guest Editorial: Field Programmable Logic. J. VLSI Signal Process. 36(1): 5-6 (2004) - [j9]Prashant Jain, Andrew Laffely, Wayne P. Burleson, Russell Tessier, Dennis Goeckel:
Dynamically Parameterized Algorithms and Architectures to Exploit Signal Variations. J. VLSI Signal Process. 36(1): 27-40 (2004) - [c22]Jian Liang, Russell Tessier, Dennis Goeckel:
A Dynamically-Reconfigurable, Power-Efficient Turbo Decoder. FCCM 2004: 91-100 - [e3]Russell Tessier, Herman Schmit:
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, California, USA, February 22-24, 2004. ACM 2004, ISBN 1-58113-829-6 [contents] - 2003
- [j8]Srini Krishnamoorthy, Russell Tessier:
Technology mapping algorithms for hybrid FPGAs containing lookup tables and PLAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(5): 545-559 (2003) - [c21]Weifeng Xu, Ramshankar Ramanarayanan, Russell Tessier:
Adaptive Fault Recovery for Networked Reconfigurable Systems. FCCM 2003: 143- - [c20]Jian Liang, Russell Tessier, Oskar Mencer:
Floating Point Unit Generation and Evaluation for FPGAs. FCCM 2003: 185-194 - [c19]Aiyappan Natarajan, David Jasinski, Wayne P. Burleson, Russell Tessier:
A hybrid adiabatic content addressable memory for ultra low-power applications. ACM Great Lakes Symposium on VLSI 2003: 72-75 - [c18]Andrew Laffely, Jian Liang, Russell Tessier, Wayne P. Burleson:
Adaptive system on a chip (ASOC): a backbone for power-aware signal processing cores. ICIP (3) 2003: 105-108 - [c17]William N. Junek, Arun Ramanathan, Gordon Farquharson, Stephen J. Frasier, Russell Tessier, David J. McLaughlin, Mark A. Sletten, Jakov V. Toporkov:
First observations with the UMass dual-beam InSAR. IGARSS 2003: 530-532 - [e2]Steve Trimberger, Russell Tessier:
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2003, Monterey, CA, USA, February 23-25, 2003. ACM 2003, ISBN 1-58113-651-X [contents] - 2002
- [j7]Murali Kudlugi, Russell Tessier:
Static scheduling of multidomain circuits for fast functional verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(11): 1253-1268 (2002) - [j6]Ian G. Harris, Russell Tessier:
Testing and diagnosis of interconnect faults in cluster-based FPGA architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(11): 1337-1343 (2002) - [j5]Russell Tessier:
Fast placement approaches for FPGAs. ACM Trans. Design Autom. Electr. Syst. 7(2): 284-305 (2002) - [j4]Navin Vemuri, Priyank Kalla, Russell Tessier:
BDD-based logic synthesis for LUT-based FPGAs. ACM Trans. Design Autom. Electr. Syst. 7(4): 501-525 (2002) - [j3]Russell Tessier, Snigdha Jana:
Incremental compilation for parallel logic verification systems. IEEE Trans. Very Large Scale Integr. Syst. 10(5): 623-636 (2002) - [c16]Sriram Swaminathan, Russell Tessier, Dennis Goeckel, Wayne P. Burleson:
A dynamically reconfigurable adaptive viterbi decoder. FPGA 2002: 227-236 - [c15]