A Mixed-Signal RISC-V Signal Analysis SoC Generator With a 16-nm FinFET Instance.

Tue, 01 Jan 2019 00:00:00 +0100

Steven Bailey , Paul Rigge , Jaeduk Han , Richard Lin, Eric Chang , Howard Mao, Zhongkai Wang, Chick Markley, Adam M. Izraelevitz, Angie Wang, Nathan Narevsky, Woo-Rham Bae , Steve Shauck, Sergio Montano, Justin Norsworthy , Munir Razzaque , Wen Hau Ma, Akalu Lentiro, Matthew Doerflein , Darin Heckendorn, Jim McGrath, Franco DeSeta, Ronen Shoham, Mike Stellfox, Mark Snowden, Joseph Cole, Dan Fuhrman, Brian C. Richards , Jonathan Bachrach , Elad Alon, Borivoje Nikolic :
A Mixed-Signal RISC-V Signal Analysis SoC Generator With a 16-nm FinFET Instance. IEEE J. Solid State Circuits 54(10): 2786-2801 (2019)