BibTeX records: Michael De Vita

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@inproceedings{DBLP:conf/cicc/BichanTZWSGTZPL20,
  author    = {Mike Bichan and
               Clifford Ting and
               Bahram Zand and
               Jing Wang and
               Ruslana Shulyzki and
               James Guthrie and
               Katya Tyshchenko and
               Junhong Zhao and
               Alireza Parsafar and
               Eric Liu and
               Aynaz Vatankhahghadim and
               Shaham Sharifian and
               Aleksey Tyshchenko and
               Michael De Vita and
               Syed Rubab and
               Sitaraman Iyer and
               Fulvio Spagna and
               Noam Dolev},
  title     = {A 32Gb/s {NRZ} 37dB SerDes in 10nm {CMOS} to Support {PCI} Express
               Gen 5 Protocol},
  booktitle = {2020 {IEEE} Custom Integrated Circuits Conference, {CICC} 2020, Boston,
               MA, USA, March 22-25, 2020},
  pages     = {1--4},
  publisher = {{IEEE}},
  year      = {2020},
  url       = {https://doi.org/10.1109/CICC48029.2020.9075947},
  doi       = {10.1109/CICC48029.2020.9075947},
  timestamp = {Mon, 04 May 2020 10:04:38 +0200},
  biburl    = {https://dblp.org/rec/conf/cicc/BichanTZWSGTZPL20.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asscc/LiSCWTGJNISLCTV18,
  author    = {Shenggao Li and
               Fulvio Spagna and
               Ji Chen and
               Xiaoqing Wang and
               Luke Tong and
               Sujatha Gowder and
               Wenyan Jia and
               Roan Nicholson and
               Sitaraman Iyer and
               Rui Song and
               Lily Li and
               Meng{-}hung Chen and
               Amanda Tran and
               Michael De Vita and
               Deepar Govindrajan and
               Marcus Pasquarella and
               Dave Bradley and
               Frank Verdico and
               Matt Duwe and
               Eric Lee and
               Michelle Wigton},
  title     = {A Power and Area Efficient 2.5-16 Gbps Gen4 PCIe {PHY} in 10nm FinFET
               {CMOS}},
  booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2018, Tainan,
               Taiwan, November 5-7, 2018},
  pages     = {5--8},
  publisher = {{IEEE}},
  year      = {2018},
  url       = {https://doi.org/10.1109/ASSCC.2018.8579314},
  doi       = {10.1109/ASSCC.2018.8579314},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/asscc/LiSCWTGJNISLCTV18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}