BibTeX records: Joe G. Xi

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@article{DBLP:journals/vlsisp/XiD97,
  author    = {Joe G. Xi and
               Wayne Wei{-}Ming Dai},
  title     = {Useful-Skew Clock Routing with Gate Sizing for Low Power Design},
  journal   = {J. {VLSI} Signal Process.},
  volume    = {16},
  number    = {2-3},
  pages     = {163--179},
  year      = {1997},
  url       = {https://doi.org/10.1023/A:1007939023899},
  doi       = {10.1023/A:1007939023899},
  timestamp = {Wed, 20 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/vlsisp/XiD97.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/XiD96,
  author    = {Joe G. Xi and
               Wayne Wei{-}Ming Dai},
  editor    = {Thomas Pennino and
               Ellen J. Yoffa},
  title     = {Useful-Skew Clock Routing With Gate Sizing for Low Power Design},
  booktitle = {Proceedings of the 33st Conference on Design Automation, Las Vegas,
               Nevada, USA, Las Vegas Convention Center, June 3-7, 1996},
  pages     = {383--388},
  publisher = {{ACM} Press},
  year      = {1996},
  url       = {https://doi.org/10.1145/240518.240592},
  doi       = {10.1145/240518.240592},
  timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/dac/XiD96.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/XiD96,
  author    = {Joe G. Xi and
               Wayne Wei{-}Ming Dai},
  editor    = {Rob A. Rutenbar and
               Ralph H. J. M. Otten},
  title     = {Jitter-tolerant clock routing in two-phase synchronous systems},
  booktitle = {Proceedings of the 1996 {IEEE/ACM} International Conference on Computer-Aided
               Design, {ICCAD} 1996, San Jose, CA, USA, November 10-14, 1996},
  pages     = {316--320},
  publisher = {{IEEE} Computer Society / {ACM}},
  year      = {1996},
  url       = {https://doi.org/10.1109/ICCAD.1996.569719},
  doi       = {10.1109/ICCAD.1996.569719},
  timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl    = {https://dblp.org/rec/conf/iccad/XiD96.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/XiD95,
  author    = {Joe G. Xi and
               Wayne Wei{-}Ming Dai},
  editor    = {Bryan Preas},
  title     = {Buffer Insertion and Sizing Under Process Variations for Low Power
               Clock Distribution},
  booktitle = {Proceedings of the 32st Conference on Design Automation, San Francisco,
               California, USA, Moscone Center, June 12-16, 1995},
  pages     = {491--496},
  publisher = {{ACM} Press},
  year      = {1995},
  url       = {https://doi.org/10.1145/217474.217576},
  doi       = {10.1145/217474.217576},
  timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/dac/XiD95.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/ZhuDX93,
  author    = {Qing Zhu and
               Wayne Wei{-}Ming Dai and
               Joe G. Xi},
  editor    = {Michael R. Lightner and
               Jochen A. G. Jess},
  title     = {Optimal sizing of high-speed clock networks based on distributed {RC}
               and lossy transmission line models},
  booktitle = {Proceedings of the 1993 {IEEE/ACM} International Conference on Computer-Aided
               Design, 1993, Santa Clara, California, USA, November 7-11, 1993},
  pages     = {628--633},
  publisher = {{IEEE} Computer Society / {ACM}},
  year      = {1993},
  url       = {https://doi.org/10.1109/ICCAD.1993.580151},
  doi       = {10.1109/ICCAD.1993.580151},
  timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl    = {https://dblp.org/rec/conf/iccad/ZhuDX93.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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