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Jagdeep Kaur Sahani

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2020 – today

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2022
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Jagdeep Kaur Sahani, Anil Singh, Alpana Agarwal:
A 1 μs Locking Time Dual Loop ADPLL with Foreground Calibration-Based 6 ps Resolution Flash TDC in 180 nm CMOS. Circuits Syst. Signal Process. 41(3): 1299-1323 (2022)
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Jagdeep Kaur Sahani, Anil Singh, Alpana Agarwal:
A low jitter and fast locking all digital phase locked loop with flash based time to digital converter and gain calibrated voltage controlled oscillator. Int. J. Circuit Theory Appl. 50(8): 2900-2912 (2022)
2020
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Jagdeep Kaur Sahani, Anil Singh, Alpana Agarwal:
A 2.3 mW Multi-Frequency Clock Generator with -137 dBc/Hz Phase Noise VCO in 180 nm Digital CMOS Technology. J. Circuits Syst. Comput. 29(8): 2050130:1-2050130:15 (2020)
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Jagdeep Kaur Sahani, Anil Singh, Alpana Agarwal:
A Wide Frequency Range Low Jitter Integer PLL with Switch and Inverter Based CP in 0.18 μm CMOS Technology. J. Circuits Syst. Comput. 29(9): 2050142:1-2050142:22 (2020)

2010 – 2019

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2019
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Jagdeep Kaur Sahani, Anil Singh, Alpana Agarwal:
A High Resolution and Low Jitter 5-Bit Flash TDC Architecture for High Speed Intelligent Systems. IntelliSys (1) 2019: 266-275

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