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2020 – today
- 2022
[j2]Tianchen Wang
, Jiawei Zhang, Jinjun Xiong, Song Bian, Zheyu Yan, Meiping Huang, Jian Zhuang, Takashi Sato, Xiaowei Xu, Yiyu Shi:
VisualNet: An End-to-End Human Visual System Inspired Framework to Reduce Inference Latency of Deep Neural Networks. IEEE Trans. Computers 71(11): 2717-2727 (2022)- [c6]Zheyu Yan, Weiwen Jiang, Xiaobo Sharon Hu, Yiyu Shi:
RADARS: Memory Efficient Reinforcement Learning Aided Differentiable Neural Architecture Search. ASP-DAC 2022: 128-133 - [c5]Zheyu Yan, Xiaobo Sharon Hu, Yiyu Shi:
SWIM: selective write-verify for computing-in-memory neural accelerators. DAC 2022: 277-282 - [c4]Zheyu Yan, Xiaobo Sharon Hu, Yiyu Shi:
Computing-In-Memory Neural Network Accelerators for Safety-Critical Systems: Can Small Device Variations Be Disastrous? ICCAD 2022: 87:1-87:9 - [i9]Zheyu Yan, Xiaobo Sharon Hu, Yiyu Shi:
SWIM: Selective Write-Verify for Computing-in-Memory Neural Accelerators. CoRR abs/2202.08395 (2022) - [i8]Bingqian Lu, Zheyu Yan, Yiyu Shi, Shaolei Ren:
A Semi-Decoupled Approach to Fast and Optimal Hardware-Software Co-Design of Neural Accelerators. CoRR abs/2203.13921 (2022) - [i7]Zheyu Yan, Xiaobo Sharon Hu, Yiyu Shi:
On the Reliability of Computing-in-Memory Accelerators for Deep Neural Networks. CoRR abs/2205.13018 (2022) - [i6]Zheyu Yan, Xiaobo Sharon Hu, Yiyu Shi:
Computing-In-Memory Neural Network Accelerators for Safety-Critical Systems: Can Small Device Variations Be Disastrous? CoRR abs/2207.07626 (2022) - 2021
- [j1]Weiwen Jiang, Qiuwen Lou, Zheyu Yan, Lei Yang, Jingtong Hu, Xiaobo Sharon Hu, Yiyu Shi:
Device-Circuit-Architecture Co-Exploration for Computing-in-Memory Neural Accelerators. IEEE Trans. Computers 70(4): 595-605 (2021) - [c3]Zheyu Yan, Da-Cheng Juan, Xiaobo Sharon Hu, Yiyu Shi:
Uncertainty Modeling of Emerging Device based Computing-in-Memory Neural Accelerators with Application to Neural Architecture Search. ASP-DAC 2021: 859-864 - [i5]Zheyu Yan, Da-Cheng Juan, Xiaobo Sharon Hu, Yiyu Shi:
Uncertainty Modeling of Emerging Device-based Computing-in-Memory Neural Accelerators with Application to Neural Architecture Search. CoRR abs/2107.06871 (2021) - [i4]Zheyu Yan, Weiwen Jiang, Xiaobo Sharon Hu, Yiyu Shi:
RADARS: Memory Efficient Reinforcement Learning Aided Differentiable Neural Architecture Search. CoRR abs/2109.05691 (2021) - 2020
- [c2]Zheyu Yan, Yiyu Shi, Wang Liao, Masanori Hashimoto, Xichuan Zhou, Cheng Zhuo:
When Single Event Upset Meets Deep Neural Networks: Observations, Explorations, and Remedies. ASP-DAC 2020: 163-168 - [c1]Lei Yang, Zheyu Yan, Meng Li, Hyoukjun Kwon, Liangzhen Lai, Tushar Krishna, Vikas Chandra, Weiwen Jiang, Yiyu Shi:
Co-Exploration of Neural Architectures and Heterogeneous ASIC Accelerator Designs Targeting Multiple Tasks. DAC 2020: 1-6 - [i3]Lei Yang, Zheyu Yan, Meng Li, Hyoukjun Kwon, Liangzhen Lai, Tushar Krishna, Vikas Chandra, Weiwen Jiang, Yiyu Shi:
Co-Exploration of Neural Architectures and Heterogeneous ASIC Accelerator Designs Targeting Multiple Tasks. CoRR abs/2002.04116 (2020)
2010 – 2019
- 2019
- [i2]Zheyu Yan, Yiyu Shi, Wang Liao, Masanori Hashimoto, Xichuan Zhou, Cheng Zhuo:
When Single Event Upset Meets Deep Neural Networks: Observations, Explorations, and Remedies. CoRR abs/1909.04697 (2019) - [i1]Weiwen Jiang, Qiuwen Lou, Zheyu Yan, Lei Yang, Jingtong Hu, Xiaobo Sharon Hu, Yiyu Shi:
Device-Circuit-Architecture Co-Exploration for Computing-in-Memory Neural Accelerators. CoRR abs/1911.00139 (2019)
Coauthor Index
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