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2020 – today
- 2023
[j16]Martti Forsell, Jussi Roivainen, Ville Leppänen
, Jesper Larsson Träff:
Realizing multioperations and multiprefixes in Thick Control Flow processors. Microprocess. Microsystems 98: 104807 (2023)- [c50]Martti Forsell, Jussi Roivainen, Ville Leppänen, Jesper Larsson Träff:
Preliminary Performance and Memory Access Scalability Study of Thick Control Flow Processors. NorCAS 2023: 1-7 - 2022
- [j15]Martti Forsell, Sara Nikula, Jussi Roivainen, Ville Leppänen, Jesper Larsson Träff:
Performance and programmability comparison of the thick control flow architecture and current multicore processors. J. Supercomput. 78(3): 3152-3183 (2022) - 2020
- [c49]Martti Forsell, Jussi Roivainen, Jesper Larsson Träff:
Optimizing Memory Access in TCF Processors with Compute-Update Operations. IPDPS Workshops 2020: 577-586
2010 – 2019
- 2018
- [j14]Martti Forsell, Jussi Roivainen, Ville Leppänen, Jesper Larsson Träff:
Supporting concurrent memory access in TCF processor architectures. Microprocess. Microsystems 63: 226-236 (2018) - [j13]Martti Forsell, Jussi Roivainen, Ville Leppänen:
REPLICA MBTAC: multithreaded dual-mode processor. J. Supercomput. 74(5): 1911-1933 (2018) - [c48]Mikko Uitto, Martti Forsell:
Towards Energy-Efficient Adaptive Mpeg-Dash Streaming Using Hevc. ICME Workshops 2018: 1-6 - [c47]Martti Forsell, Jussi Roivainen, Ville Leppänen, Jesper Larsson Träff:
Implementation of Multioperations in Thick Control Flow Processors. IPDPS Workshops 2018: 744-752 - [p2]Martti Forsell:
Reducing Power Consumption in Mobile Terminals - Video Computing Perspective. Greening Video Distribution Networks 2018: 101-126 - 2017
- [c46]Jari-Matti Mäkelä, Martti Forsell, Ville Leppänen:
Towards a Language Framework for Thick Control Flows. IPDPS Workshops 2017: 814-823 - [c45]Martti Forsell, Jussi Roivainen, Ville Leppänen, Jesper Larsson Träff:
Supporting concurrent memory access in TCF-aware processor architectures. NORCAS 2017: 1-6 - 2016
- [c44]Mohammadhassan Safavi, Saeed Bastani, Zhi Zhang, Martti Forsell, Olli Mämmelä, Björn Landfeldt:
A study on energy used to deliver H.264/AVC and H.265/HEVC video content. CAMAD 2016: 170-176 - [c43]Jari-Matti Mäkelä, Martti Forsell, Ville Leppänen:
Compiler assisted dynamic allocation of finite hardware acceleration resources for parallel tasks. CompSysTech 2016: 49-56 - [c42]Martti Forsell, Jussi Roivainen, Ville Leppänen:
The REPLICA on-chip network. NORCAS 2016: 1-6 - [c41]Martti Forsell, Jussi Roivainen, Ville Leppänen:
Outline of a Thick Control Flow Architecture. SBAC-PAD (Workshops) 2016: 1-6 - 2015
- [c40]Martti Forsell, Ville Leppänen, Martti Penttonen:
Cost of Bandwidth-Optimized Sparse Mesh Layouts. PaCT 2015: 375-389 - 2014
- [j12]Martti Forsell, Erik Hansson, Christoph W. Kessler, Jari-Matti Mäkelä, Ville Leppänen:
NUMA Computing with Hardware and Software Co-Support on Configurable Emulated Shared Memory Architectures. Int. J. Netw. Comput. 4(1): 189-206 (2014) - [c39]Thomas Canhao Xu, Ville Leppänen, Martti Forsell:
Exploration of a Heterogeneous Concentrated-Sparse On-Chip Interconnect for Energy Efficient Multicore Architecture. CIT 2014: 204-211 - [c38]Martti Forsell, Jussi Roivainen:
REPLICA T7-16-128 - A 2048-threaded 16-core 7-FU chained VLIW chip multiprocessor. ACSSC 2014: 1709-1713 - [c37]Erik Hansson, Erik Alnervik, Christoph W. Keßler, Martti Forsell:
A Quantitative Comparison of PRAM based Emulated Shared Memory Architectures to Current Multicore CPUs and GPUs. ARCS Workshops 2014: 1-7 - [c36]Martti Forsell, Jussi Roivainen, Ville Leppänen:
Prototyping the MBTAC Processor for the REPLICA CMP. IPDPS Workshops 2014: 709-716 - 2013
- [j11]Martti Forsell, Ville Leppänen:
An Extended PRAM-NUMA Model of Computation for TCF Programming. Int. J. Netw. Comput. 3(1): 98-115 (2013) - [c35]Jari-Matti Mäkelä, Ville Leppänen, Martti Forsell:
Towards a parallel debugging framework for the massively multi-threaded, step-synchronous REPLICA architecture. CompSysTech 2013: 153-160 - [c34]Thomas Canhao Xu, Ville Leppänen, Martti Forsell:
DSNOC: A Hybrid Dense-Sparse Network-on-Chip Architecture for Efficient Scalable Computing. DASC 2013: 528-535 - [c33]Martti Forsell, Erik Hansson, Christoph W. Kessler, Jari-Matti Mäkelä, Ville Leppänen:
Hardware and Software Support for NUMA Computing on Configurable Emulated Shared Memory Architectures. IPDPS Workshops 2013: 640-648 - 2012
- [c32]Jari-Matti Mäkelä, Ville Leppänen, Martti Forsell:
Preliminary analysis of feasible benchmark problems for the hydrid PRAM/NUMA REPLICA architecture. CompSysTech 2012: 37-44 - [c31]Martti Forsell, Mikko Hiivala:
Multi-core Portability Abstraction. IPDPS Workshops 2012: 778-785 - [c30]Martti Forsell, Ville Leppänen:
An Extended PRAM-NUMA Model of Computation for TCF Programming. IPDPS Workshops 2012: 786-793 - [c29]Jari-Matti Mäkelä, Erik Hansson, Daniel Åkesson, Martti Forsell, Christoph W. Kessler, Ville Leppänen:
Design of the Language Replica for Hybrid PRAM-NUMA Many-core Architectures. ISPA 2012: 697-704 - 2011
- [j10]Martti Forsell:
A PRAM-NUMA Model of Computation for Addressing Low-TLP Workloads. Int. J. Netw. Comput. 1(1): 21-35 (2011) - [j9]Martti Forsell:
Performance comparison of some shared memory organizations for 2D mesh-like NOCs. Microprocess. Microsystems 35(2): 274-284 (2011) - [j8]Martti Forsell, Ville Leppänen:
A moving threads processor architecture MTPA. J. Supercomput. 57(1): 5-19 (2011) - [c28]Ville Leppänen, Martti Penttonen, Martti Forsell:
A layout for sparse cube-connected-cycles network. CompSysTech 2011: 32-37 - [c27]Jari-Matti Mäkelä, Ville Leppänen, Martti Forsell:
RISC-based moving threads multicore architecture. CompSysTech 2011: 51-56 - [c26]Martti Forsell, Ville Leppänen, Martti Penttonen:
Cost of Sparse Mesh Layouts Supporting Throughput Computing. DSD 2011: 316-323 - 2010
- [j7]Martti Forsell:
On the Performance and Cost of Some PRAM Models on CMP Hardware. Int. J. Found. Comput. Sci. 21(3): 387-404 (2010) - [c25]Martti Forsell, Jesper Larsson Träff:
HPPC 2010: Forth Workshop on Highly Parallel Processing on a Chip. Euro-Par Workshops 2010: 73-75 - [c24]Martti Forsell, Jesper Larsson Träff:
HPPC 2010: 5th Workshop on Highly Parallel Processing on a Chip. Euro-Par Workshops (1) 2010: 245-247 - [c23]Martti Forsell:
A PRAM-NUMA model of computation for addressing low-TLP workloads. IPDPS Workshops 2010: 1-8 - [c22]Martti Forsell, Ville Leppänen:
Supporting Concurrent Memory Access and Multioperations in Moving Threads CMPs. PDPTA 2010: 377-383 - [c21]Ville Leppänen, Martti Penttonen, Martti Forsell:
Layouts for Sparse Networks Supporting Throughput Computing. PDPTA 2010: 443-449 - [e2]Hai-Xiang Lin, Michael Alexander, Martti Forsell, Andreas Knüpfer, Radu Prodan, Leonel Sousa, Achim Streit:
Euro-Par 2009 - Parallel Processing Workshops, HPPC, HeteroPar, PROPER, ROIA, UNICORE, VHPC, Delft, The Netherlands, August 25-28, 2009, Revised Selected Papers. Lecture Notes in Computer Science 6043, Springer 2010, ISBN 978-3-642-14121-8 [contents]
2000 – 2009
- 2009
- [c20]Jani Paakkulainen, Jari-Matti Mäkelä, Ville Leppänen, Martti Forsell:
Outline of RISC-based core for multiprocessor on chip architecture supporting moving threads. CompSysTech 2009: 11 - [c19]Martti Forsell, Jesper Larsson Träff:
HPPC 2009: 3rd Workshop on Highly Parallel Processing on a Chip. Euro-Par Workshops 2009: 3-5 - [c18]Martti Forsell, H. Peter Hofstee, Ahmed Jerraya, Chris R. Jesshope, Uzi Vishkin, Jesper Larsson Träff:
HPPC 2009 Panel: Are Many-Core Computer Vendors on Track? Euro-Par Workshops 2009: 9-15 - [c17]Martti Forsell:
Configurable emulated shared memory architecture for general purpose MP-SOCs and NOC regions. NOCS 2009: 163-172 - [c16]Martti Forsell, Ville Leppänen:
MTPA - A Processor Architecture for MP-SOCs Employing the Moving Threads Paradigm. PDPTA 2009: 198-204 - 2008
- [c15]Martti Forsell, Jesper Larsson Träff:
Second Workshop on Highly Parallel Processing on a Chip (HPPC 2008). Euro-Par Workshops 2008: 123-125 - [c14]Martti Forsell:
On the performance and cost of some PRAM models on CMP hardware. IPDPS 2008: 1-8 - [c13]Martti Forsell, Jussi Roivainen:
Performance, Area and Power Trade-Offs in Mesh-based Emulated Shared Memory CMP Architectures. PDPTA 2008: 471-477 - [e1]Luc Bougé, Martti Forsell, Jesper Larsson Träff, Achim Streit, Wolfgang Ziegler, Michael Alexander, Stephen Childs:
Euro-Par 2007 Workshops: Parallel Processing, HPPC 2007, UNICORE Summit 2007, and VHPC 2007, Rennes, France, August 28-31, 2007, Revised Selected Papers. Lecture Notes in Computer Science 4854, Springer 2008, ISBN 978-3-540-78472-2 [contents] - 2007
- [c12]Martti Forsell, Jesper Larsson Träff:
HPPC 2007: Workshop on Highly Parallel Processing on a Chip. Euro-Par Workshops 2007: 3-4 - [c11]Martti Forsell, Ville Leppänen:
Moving Threads: A Non-Conventional Approach for Mapping Computation to MP-SOC. PDPTA 2007: 232-238 - 2006
- [c10]Martti Forsell:
Reducing the associativity and size of step caches in CRCW operation. IPDPS 2006 - [c9]Martti Forsell:
Realizing Multioperations for Step Cached MP-SOCs. SoC 2006: 1-6 - 2005
- [j6]Martti Forsell:
Realising constant time parallel algorithms with active memory modules. Int. J. Electron. Bus. 3(3/4): 255-263 (2005) - [c8]Martti Forsell:
ParLe - A Parallel Computing Learning Set for MPSOCs/NOCs. SoC 2005: 90-95 - 2004
- [c7]Martti Forsell:
Designing NOCs with a parallel extension of c. FDL 2004: 463-475 - [c6]Martti Forsell:
Efficient barrier synchronization mechanism for emulated shared memory NOCs. SoC 2004: 33-36 - [c5]Martti Forsell:
Ec - a compiler for the e-language [NOC applications]. SoC 2004: 157-160 - 2003
- [c4]Juha-Pekka Soininen, Axel Jantsch, Martti Forsell, Antti Pelkonen, Jari Kreku, Shashi Kumar:
Extending Platform-Based Design to Network on Chip Systems. VLSI Design 2003: 401- - [p1]Martti Forsell:
A Parallel Computer as a NOC Region. Networks on Chip 2003: 173-192 - 2002
- [j5]Martti Forsell:
Architectural differences of efficient sequential and parallel computers. J. Syst. Archit. 47(13): 1017-1041 (2002) - [j4]Martti Forsell:
A Scalable High-Performance Computing Solution for Networks on Chips. IEEE Micro 22(5): 46-55 (2002) - [j3]Eugene I. Ageenko, Martti Forsell, Pasi Fränti:
Context-based compression of binary images in parallel. Softw. Pract. Exp. 32(13): 1223-1237 (2002) - [c3]Juha-Pekka Soininen, Jari Kreku, Yang Qu, Martti Forsell:
Fast processor core selection for WLAN modem using mappability estimation. CODES 2002: 61-66 - [c2]Shashi Kumar, Axel Jantsch, Mikael Millberg, Johnny Öberg, Juha-Pekka Soininen, Martti Forsell, Kari Tiensyrjä, Ahmed Hemani:
A Network on Chip Architecture and Design Methodology. ISVLSI 2002: 117-124
1990 – 1999
- 1997
- [j2]Martti Forsell:
MTAC - A Multithreaded VLIW Architecture for PRAM Simulation. J. Univers. Comput. Sci. 3(9): 1037-1055 (1997) - 1996
- [j1]Martti Forsell:
Minimal pipeline architecture - an alternative to superscalar architecture. Microprocess. Microsystems 20(5): 277-284 (1996) - [c1]Martti Forsell, Martti Penttonen, Ville Leppänen:
Efficient Two-Level Mesh based Simulation of PRAMs. ISPAN 1996: 29-35
Coauthor Index
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last updated on 2024-08-05 20:25 CEST by the dblp team
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