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2020 – today
- 2025
[i5]Paresh Baidya, Rourab Paul, Vikas Srivastava, Sumit Kumar Debnath:
Energy-Efficient NTT Sampler for Kyber Benchmarked on FPGA. CoRR abs/2505.01782 (2025)- [i4]Rourab Paul, Paresh Baidya, Krishnendu Guha:
Lightweight Fault Detection Architecture for NTT on FPGA. CoRR abs/2508.03062 (2025) - [i3]Paresh Baidya, Rourab Paul, Vikas Srivastava, Sumit Kumar Debnath:
Error Detection Schemes for Barrett Reduction of CT-BU on FPGA in Post Quantum Cryptography. CoRR abs/2509.04070 (2025) - 2024
- [j2]Paresh Baidya
, Swagata Mandal, Rourab Paul:
Near Threshold Computation of Partitioned Ring Learning With Error (RLWE) Hardware Accelerator on Reconfigurable Architecture. IEEE Access 12: 68814-68827 (2024) - [j1]Paresh Baidya, Rourab Paul, Swagata Mandal, Sumit Kumar Debnath:
Efficient Implementation of Knuth Yao Sampler on Reconfigurable Hardware. IEEE Comput. Archit. Lett. 23(2): 195-198 (2024) - 2023
- [i2]Vikas Srivastava, Paresh Baidya, Sumit Kumar Debnath, Sihem Mesnager:
Blockchain-Envisioned Post-Quantum Secure Sanitizable Signature for Audit Logs Management. CoRR abs/2312.16322 (2023) - 2022
- [i1]Paresh Baidya, Swagata Mandal, Rourab Paul:
Near Threshold Computation of Partitioned Ring Learning With Error (RLWE) Post Quantum Cryptography on Reconfigurable Architecture. CoRR abs/2208.08093 (2022)
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