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2020 – today
- 2024
[j3]Kewei Xin
, Mingche Lai, Fangxu Lv, Xuqiang Zheng, Kaile Guo, Zhengbin Pang, Chaolong Xu, Geng Zhang, Wenchen Wang, Meng Li:
Frequency Domain Modeling and Performance Analysis of Injection-Locked LC Oscillator. IEEE Trans. Circuits Syst. II Express Briefs 71(1): 11-15 (2024)- [c2]Chaolong Xu, Fangxu Lv, Zhengbin Pang, Liquan Xiao, Zhouhao Yang:
FPGA Implementation of Sequence Detector for High-Speed PAM4 Wireline Transceiver. ACM Great Lakes Symposium on VLSI 2024: 13-18 - 2023
- [c1]Mingche Lai, Fangxu Lv, Geng Zhang, Chaolong Xu:
A Low BER Cooperative-adaptive-equalizer for Serial Receiver in HPC Networks. HPCC/DSS/SmartCity/DependSys 2023: 742-749 - 2022
- [j2]Geng Zhang, Mingche Lai, Fangxu Lyu, Xuqiang Zheng, Heming Wang, Dongbin Lv, Chaolong Xu, Xingyun Qi, Qing Liu:
A CNRZ-7 Based Wireline Transceiver With High-Bandwidth-Density, Low-Power for D2D Communication. IEEE Access 10: 96556-96567 (2022) - [j1]Mingche Lai, Geng Zhang, Fangxu Lv, Xuqiang Zheng, Heming Wang, Dongbin Lv, Chaolong Xu, Xingyun Qi:
A 33.33 Gb/s/wire pin-efficient 1.06 pJ/bit wireline transceiver based on CNRZ-5 for Chiplet in 28 nm CMOS. Microelectron. J. 130: 105628 (2022)
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