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ORCIDTam-Anh Chu
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1990 – 1999
- 1995
[j5]Tam-Anh Chu, Rabindra K. Roy:
Guest Editors' Introduction: More Practical Asynchronous Design. IEEE Des. Test Comput. 12(1): 13- (1995)- 1994
- [j4]Tam-Anh Chu, Rabindra K. Roy:
Guest Editor's Introduction: Practical Asynchronous Design. IEEE Des. Test Comput. 11(2): 6-7 (1994) - [j3]Tam-Anh Chu:
Synthesis of hazard-free control circuits from asynchronous finite state machines specifications. J. VLSI Signal Process. 7(1-2): 61-84 (1994) - 1993
- [j2]Tam-Anh Chu:
CLASS: a CAD system for automatic synthesis and verification of asynchronous finite state machines. Integr. 15(3): 263-289 (1993) - [c7]Tam Anh Chu, Huy T. Cao, Clement K. C. Leung:
ESP: An Executable Specification Language for Mixed Timing Control Circuits. CHDL 1993: 417-434 - [c6]Tam Anh Chu, Narayana Mani, Clement K. C. Leung:
An Efficient Critical Race-Free State Assignment Technique for Asynchronous Finite State Machines. DAC 1993: 2-6 - [c5]Tam Anh Chu, Narayana Mani, Clement K. C. Leung:
A new state assignment technique for asynchronous finite state machines. Great Lakes Symposium on VLSI 1993: 139-143 - [c4]Tam Anh Chu:
On the Specification and Synthesis of Hazard-free Asynchronous Control Circuits. ISCAS 1993: 1495-1498 - 1992
- [c3]Tam-Anh Chu:
Automatic Synthesis and Verification of Hazard-Free Control Circuits from Asynchronous Finite State Machine Specifications. ICCD 1992: 407-413
1980 – 1989
- 1987
- [b1]Tam-Anh Chu:
Synthesis of self-timed VLSI circuits from graph-theoretic specifications. Massachusetts Institute of Technology, Cambridge, MA, USA, 1987 - [c2]Tam-Anh Chu:
A Method of Abstraction for Petri Nets. PNPM 1987: 164-173 - 1986
- [j1]Tam-Anh Chu:
On the models for designing VLSI asynchronous digital systems. Integr. 4(2): 99-113 (1986) - [c1]Tam Anh Chu, Clement K. C. Leung:
Design of VLSI Asynchronous FIFO Queues for Packet Communication Networks. ICPP 1986: 397-400
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