BibTeX records: Mu-Shan Lin

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@article{DBLP:journals/jssc/LinHTTHCHHCGFRL20,
  author    = {Mu{-}Shan Lin and
               Tze{-}Chiang Huang and
               Chien{-}Chun Tsai and
               King{-}Ho Tam and
               Kenny Cheng{-}Hsiang Hsieh and
               Ching{-}Fang Chen and
               Wen{-}Hung Huang and
               Chi{-}Wei Hu and
               Yu{-}Chi Chen and
               Sandeep Kumar Goel and
               Chin{-}Ming Fu and
               Stefan Rusu and
               Chao{-}Chieh Li and
               Sheng{-}Yao Yang and
               Mei Wong and
               Shu{-}Chun Yang and
               Frank Lee},
  title     = {A 7-nm 4-GHz Arm{\({^1}\)}-Core-Based CoWoS{\({^1}\)} Chiplet Design
               for High-Performance Computing},
  journal   = {{IEEE} J. Solid State Circuits},
  volume    = {55},
  number    = {4},
  pages     = {956--966},
  year      = {2020},
  url       = {https://doi.org/10.1109/JSSC.2019.2960207},
  doi       = {10.1109/JSSC.2019.2960207},
  timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/jssc/LinHTTHCHHCGFRL20.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsic/LinHTTHCHHCGFRL19,
  author    = {Mu{-}Shan Lin and
               Tze{-}Chiang Huang and
               Chien{-}Chun Tsai and
               King{-}Ho Tam and
               Kenny Cheng{-}Hsiang Hsieh and
               Tom Chen and
               Wen{-}Hung Huang and
               Jack Hu and
               Yu{-}Chi Chen and
               Sandeep Kumar Goel and
               Chin{-}Ming Fu and
               Stefan Rusu and
               Chao{-}Chieh Li and
               Sheng{-}Yao Yang and
               Mei Wong and
               Shu{-}Chun Yang and
               Frank Lee},
  title     = {A 7nm 4GHz Arm\({}^{\mbox{{\textregistered}}}\)-core-based CoWoS\({}^{\mbox{{\textregistered}}}\)
               Chiplet Design for High Performance Computing},
  booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
  pages     = {28},
  publisher = {{IEEE}},
  year      = {2019},
  url       = {https://doi.org/10.23919/VLSIC.2019.8778161},
  doi       = {10.23919/VLSIC.2019.8778161},
  timestamp = {Thu, 02 Apr 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/vlsic/LinHTTHCHHCGFRL19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/hotchips/LinTHHCYFZCLCKT16,
  author    = {Mu{-}Shan Lin and
               Chien{-}Chun Tsai and
               Kenny Cheng{-}Hsiang Hsieh and
               Wen{-}Hung Huang and
               Yu{-}Chi Chen and
               Shu{-}Chun Yang and
               Chin{-}Ming Fu and
               Hao{-}Jie Zhan and
               Jinn{-}Yeh Chien and
               Shao{-}Yu Li and
               Y.{-}H. Chen and
               C.{-}C. Kuo and
               Shih{-}Peng Tai and
               Kazuyoshi Yamada},
  title     = {A 16nm 256-bit wide 89.6GByte/s total bandwidth in-package interconnect
               with 0.3V swing and 0.062pJ/bit power in InFO package},
  booktitle = {2016 {IEEE} Hot Chips 28 Symposium (HCS), Cupertino, CA, USA, August
               21-23, 2016},
  pages     = {1--32},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/HOTCHIPS.2016.7936211},
  doi       = {10.1109/HOTCHIPS.2016.7936211},
  timestamp = {Thu, 02 Apr 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/hotchips/LinTHHCYFZCLCKT16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/LinTCHHYFCHCHAWSM14,
  author    = {Mu{-}Shan Lin and
               Chien{-}Chun Tsai and
               Chih{-}Hsien Chang and
               Wen{-}Hung Huang and
               Ying{-}Yu Hsu and
               Shu{-}Chun Yang and
               Chin{-}Ming Fu and
               Mao{-}Hsuan Chou and
               Tien{-}Chien Huang and
               Ching{-}Fang Chen and
               Tze{-}Chiang Huang and
               Saman Adham and
               Min{-}Jer Wang and
               William Wu Shen and
               Ashok Mehta},
  title     = {A 1 Tbit/s Bandwidth 1024 b PLL/DLL-Less eDRAM {PHY} Using 0.3 {V}
               0.105 mW/Gbps Low-Swing {IO} for CoWoS Application},
  journal   = {{IEEE} J. Solid State Circuits},
  volume    = {49},
  number    = {4},
  pages     = {1063--1074},
  year      = {2014},
  url       = {https://doi.org/10.1109/JSSC.2013.2297399},
  doi       = {10.1109/JSSC.2013.2297399},
  timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/jssc/LinTCHHYFCHCHAWSM14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/cicc/ChenTCPHYCHLLFYWCWWP10,
  author    = {Wei{-}Chih Chen and
               Chien{-}Chun Tsai and
               Chih{-}Hsien Chang and
               Yung{-}Chow Peng and
               Fu{-}Lung Hsueh and
               Tsung{-}Hsin Yu and
               Jinn{-}Yeh Chien and
               Wen{-}Hung Huang and
               Chi{-}Chang Lu and
               Mu{-}Shan Lin and
               Chin{-}Ming Fu and
               Shu{-}Chun Yang and
               Chung{-}Wing Wong and
               Wan{-}Te Chen and
               Chin{-}Hua Wen and
               Li Yueh Wang and
               Chiang Pu},
  editor    = {Jacqueline Snyder and
               Rakesh Patel and
               Tom Andre},
  title     = {A 2.5-8Gb/s transceiver with 5-tap {DFE} and Second order {CDR} against
               28-inch channel and 5000ppm {SSC} in 40nm {CMOS} technology},
  booktitle = {{IEEE} Custom Integrated Circuits Conference, {CICC} 2010, San Jose,
               California, USA, 19-22 September, 2010, Proceedings},
  pages     = {1--4},
  publisher = {{IEEE}},
  year      = {2010},
  url       = {https://doi.org/10.1109/CICC.2010.5617469},
  doi       = {10.1109/CICC.2010.5617469},
  timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
  biburl    = {https://dblp.org/rec/conf/cicc/ChenTCPHYCHLLFYWCWWP10.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}