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ORCIDJames C. Hoe
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- affiliation: Carnegie Mellon University, Pittsburgh, USA
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2020 – today
- 2023
[j24]Zhipeng Zhao
, Joseph Melber, Siddharth Sahay, Shashank Obla, Eriko Nurvitadhi, James C. Hoe:
Exploiting the Common Case When Accelerating Input-Dependent Stream Processing by FPGA. IEEE Trans. Computers 72(5): 1343-1355 (2023)- [c87]Hugo Sadok, Nirav Atre, Zhipeng Zhao, Daniel S. Berger, James C. Hoe, Aurojit Panda, Justine Sherry, Ren Wang:
Ensō: A Streaming Interface for NIC-Application Communication. OSDI 2023: 1005-1025 - [i6]Maruti K. Mudunuru, James A. Ang, Mahantesh Halappanavar, Simon D. Hammond, Maya B. Gokhale, James C. Hoe, Tushar Krishna, Sarat Sreepathi, Matthew R. Norman, Ivy Bo Peng, Philip W. Jones:
Perspectives on AI Architectures and Co-design for Earth System Predictability. CoRR abs/2304.03748 (2023) - 2022
- [c86]Guanglin Xu, James C. Hoe, Franz Franchetti:
Flexible Hardware Accelerator Design Generation with Spiral. HPEC 2022: 1-7 - [c85]Zhipeng Zhao, Nirav Atre, Hugo Sadok, Siddharth Sahay, Shashank Obla, James C. Hoe, Justine Sherry:
Pigasus 2.0: making the pigasus IDS robust to attacks and different workloads. SIGCOMM Posters and Demos 2022: 61-62 - 2021
- [c84]Daming D. Chen, Wen Shih Lim, Mohammad Bakhshalipour, Phillip B. Gibbons, James C. Hoe, Bryan Parno:
HerQules: securing programs via hardware-enforced message queues. ASPLOS 2021: 773-788 - [c83]Hugo Sadok, Zhipeng Zhao, Valerie Choung, Nirav Atre, Daniel S. Berger, James C. Hoe, Aurojit Panda, Justine Sherry:
We need kernel interposition over the network dataplane. HotOS 2021: 152-158 - [i5]Daehyeok Kim, Nikita Lazarev, Tommy Tracy II, Farzana Siddique, Hun Namkung, James C. Hoe, Vyas Sekar, Kevin Skadron, Zhiru Zhang, Srinivasan Seshan:
A Roadmap for Enabling a Future-Proof In-Network Computing Data Plane Ecosystem. CoRR abs/2111.04563 (2021) - 2020
- [j23]Peter F. Klemperer, Hye Yoon Jeon, Bryan D. Payne, James C. Hoe:
High-Performance Memory Snapshotting for Real-Time, Consistent, Hypervisor-Based Monitors. IEEE Trans. Dependable Secur. Comput. 17(3): 518-535 (2020) - [c82]Joseph Melber, James C. Hoe:
A Service-Oriented Memory Architecture for FPGA Computing. FPL 2020: 91-97 - [c81]Marie Nguyen, Nathan Serafin, James C. Hoe:
Partial Reconfiguration for Design Optimization. FPL 2020: 328-334 - [c80]Andrew Boutros, Eriko Nurvitadhi, Rui Ma, Sergey Gribok, Zhipeng Zhao, James C. Hoe, Vaughn Betz, Martin Langhammer:
Beyond Peak Performance: Comparing the Real Performance of AI-Optimized FPGAs and GPUs. FPT 2020: 10-19 - [c79]Zhipeng Zhao, Hugo Sadok, Nirav Atre, James C. Hoe, Vyas Sekar, Justine Sherry:
Achieving 100Gbps Intrusion Prevention on a Single Server. OSDI 2020: 1083-1100 - [i4]Marie Nguyen, Nathan Serafin, James C. Hoe:
Partial Reconfiguration for Design Optimization. CoRR abs/2008.00062 (2020)
2010 – 2019
- 2019
- [c78]Yu Wang, James C. Hoe, Eriko Nurvitadhi:
Processor Assisted Worklist Scheduling for FPGA Accelerated Graph Processing on a Shared-Memory Platform. FCCM 2019: 136-144 - [c77]Marie Nguyen, Robert Tamburo, Srinivasa G. Narasimhan, James C. Hoe:
Quantifying the Benefits of Dynamic Partial Reconfiguration for Embedded Vision Applications. FPL 2019: 129-135 - [c76]Fazle Sadi, Joe Sweeney, Tze Meng Low, James C. Hoe, Larry T. Pileggi, Franz Franchetti:
Efficient SpMV Operation for Large and Highly Sparse Matrices using Scalable Multi-way Merge Parallelization. MICRO 2019: 347-358 - 2018
- [j22]Franz Franchetti, Tze Meng Low, Doru-Thom Popovici, Richard Michael Veras, Daniele G. Spampinato, Jeremy R. Johnson, Markus Püschel, James C. Hoe, José M. F. Moura:
SPIRAL: Extreme Performance Portability. Proc. IEEE 106(11): 1935-1968 (2018) - [c75]Marie Nguyen, James C. Hoe:
Time-Shared Execution of Realtime Computer Vision Pipelines by Dynamic Partial Reconfiguration. FPL 2018: 230-234 - [c74]Fazle Sadi, Joe Sweeney, Scott McMillan, Tze Meng Low, James C. Hoe, Larry T. Pileggi, Franz Franchetti:
PageRank Acceleration for Large Graphs with Scalable Hardware and Two-Step SpMV. HPEC 2018: 1-7 - [i3]Marie Nguyen, James C. Hoe:
Time-Shared Execution of Realtime Streaming Pipelines by Dynamic Partial Reconfiguration. CoRR abs/1805.10431 (2018) - 2017
- [c73]Zhipeng Zhao, James C. Hoe:
Using Vivado-HLS for Structural Design: a NoC Case Study (Abstract Only). FPGA 2017: 289 - [i2]Marie Nguyen, James C. Hoe:
Amorphous Dynamic Partial Reconfiguration with Flexible Boundaries to Remove Fragmentation. CoRR abs/1710.08270 (2017) - [i1]Zhipeng Zhao, James C. Hoe:
Using Vivado-HLS for Structural Design: a NoC Case Study. CoRR abs/1710.10290 (2017) - 2016
- [j21]James C. Hoe:
FPGA compute acceleration is first about energy efficiency: technical perspective. Commun. ACM 59(11): 113 (2016) - [j20]Berkin Akin, Franz Franchetti, James C. Hoe:
HAMLeT Architecture for Parallel Data Reorganization in Memory. IEEE Micro 36(1): 14-23 (2016) - [j19]Berkin Akin, Franz Franchetti, James C. Hoe:
FFTs with Near-Optimal Memory Access Through Block Data Layouts: Algorithm, Architecture and Design Automation. J. Signal Process. Syst. 85(1): 67-82 (2016) - [c72]Gabriel Weisz, Joseph Melber, Yu Wang, Kermin Fleming, Eriko Nurvitadhi, James C. Hoe:
A Study of Pointer-Chasing Performance on Shared-Memory Processor-FPGA Systems. FPGA 2016: 264-273 - [p1]Hyun Soo Park, Yu Wang, Eriko Nurvitadhi, James C. Hoe, Yaser Sheikh, Mei Chen:
3D Point Cloud Reduction Using Mixed-Integer Quadratic Programming. Large-Scale Visual Geo-Localization 2016: 189-203 - 2015
- [j18]Michael K. Papamichael, James C. Hoe:
The CONNECT Network-on-Chip Generator. Computer 48(12): 72-79 (2015) - [c71]Michael K. Papamichael, Peter A. Milder, James C. Hoe:
Nautilus: fast automated IP design space search using guided genetic algorithms. DAC 2015: 43:1-43:6 - [c70]Gabriel Weisz, James C. Hoe:
CoRAM++: Supporting data-structure-specific memory interfaces for FPGA computing. FPL 2015: 1-8 - [c69]Berkin Akin, Franz Franchetti, James C. Hoe:
Data reorganization in memory using 3D-stacked DRAM. ISCA 2015: 131-143 - [c68]Michael Papamichael, Cagla Cakir, Chen Sun, Chia-Hsin Owen Chen, James C. Hoe, Ken Mai, Li-Shiuan Peh, Vladimir Stojanovic:
DELPHI: a framework for RTL-based architecture design evaluation using DSENT models. ISPASS 2015: 11-20 - [c67]Qi Guo, Tze Meng Low, Nikolaos Alachiotis, Berkin Akin, Larry T. Pileggi, James C. Hoe, Franz Franchetti:
Enabling portable energy efficiency with memory accelerated library. MICRO 2015: 750-761 - 2014
- [b2]Hari Angepat, Derek Chiou, Eric S. Chung, James C. Hoe:
FPGA-Accelerated Simulation of Computer Systems. Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers 2014, ISBN 978-3-031-00616-6 - [c66]Berkin Akin, Franz Franchetti, James C. Hoe:
Understanding the design space of DRAM-optimized hardware FFT accelerators. ASAP 2014: 248-255 - [c65]Eriko Nurvitadhi, Gabriel Weisz, Yu Wang, Skand Hurkat, Marie Nguyen, James C. Hoe, José F. Martínez, Carlos Guestrin:
GraphGen: An FPGA Framework for Vertex-Centric Graph Computation. FCCM 2014: 25-28 - [c64]Berkin Akin, James C. Hoe, Franz Franchetti:
HAMLeT: Hardware accelerated memory layout transform within 3D-stacked DRAM. HPEC 2014: 1-6 - [c63]Fazle Sadi, Berkin Akin, Doru-Thom Popovici, James C. Hoe, Larry T. Pileggi, Franz Franchetti:
Algorithm/hardware co-optimized SAR image reconstruction with 3D-stacked logic in memory. HPEC 2014: 1-6 - [c62]Berkin Akin, Franz Franchetti, James C. Hoe:
FFTS with near-optimal memory access through block data layouts. ICASSP 2014: 3898-3902 - [c61]Nicolas Ventroux, Julien Peeters, Tanguy Sassolas, James C. Hoe:
Highly-parallel special-purpose multicore architecture for SystemC/TLM simulations. ICSAMOS 2014: 250-257 - 2013
- [c60]Qiuling Zhu, Berkin Akin, Huseyin Ekin Sumbul, Fazle Sadi, James C. Hoe, Larry T. Pileggi, Franz Franchetti:
A 3D-stacked logic-in-memory accelerator for application-specific data intensive computing. 3DIC 2013: 1-7 - [c59]Hyun Soo Park, Yu Wang, Eriko Nurvitadhi, James C. Hoe, Yaser Sheikh, Mei Chen:
3D Point Cloud Reduction Using Mixed-Integer Quadratic Programming. CVPR Workshops 2013: 229-236 - [c58]Eric S. Chung, Michael Papamichael, Gabriel Weisz, James C. Hoe:
Cross-platform FPGA accelerator development using CoRAM and CONNECT. FPGA 2013: 3-4 - [c57]Gabriel Weisz, James C. Hoe:
C-to-CoRAM: compiling perfect loop nests to the portable CoRAM abstraction. FPGA 2013: 221-230 - 2012
- [j17]Peter A. Milder, Franz Franchetti, James C. Hoe, Markus Püschel:
Computer Generation of Hardware for Linear Digital Signal Processing Transforms. ACM Trans. Design Autom. Electr. Syst. 17(2): 15:1-15:33 (2012) - [c56]Berkin Akin, Peter A. Milder, Franz Franchetti, James C. Hoe:
Memory Bandwidth Efficient Two-Dimensional Fast Fourier Transform Algorithm and Implementation for Large Problem Sizes. FCCM 2012: 188-191 - [c55]Michael Papamichael, James C. Hoe:
CONNECT: re-examining conventional wisdom for designing nocs in the context of FPGAs. FPGA 2012: 37-46 - [c54]Eric S. Chung, Michael Papamichael, Gabriel Weisz, James C. Hoe, Ken Mai:
Prototype and evaluation of the CoRAM memory architecture for FPGA-based computing. FPGA 2012: 139-142 - [c53]Berkin Akin, Peter A. Milder, Franz Franchetti, James C. Hoe:
Algorithm and architecture optimization for large size two dimensional discrete fourier transform (abstract only). FPGA 2012: 271 - [c52]Robert Koutsoyannis, Peter A. Milder, Christian R. Berger, Madeleine Glick, James C. Hoe, Markus Püschel:
Improving fixed-point accuracy of FFT cores in O-OFDM systems. ICASSP 2012: 1585-1588 - [c51]Wei Yu, Franz Franchetti, James C. Hoe, Tsuhan Chen:
Highly Efficient Performance Portable Tracking of Evolving Surfaces. IPDPS 2012: 296-307 - 2011
- [j16]Orathai Sukwong, Hyong S. Kim, James C. Hoe:
Commercial Antivirus Software Effectiveness: An Empirical Study. Computer 44(3): 63-70 (2011) - [j15]Eriko Nurvitadhi, James C. Hoe, Timothy Kam, Shih-Lien Lu:
Automatic Pipelining From Transactional Datapath Specifications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(3): 441-454 (2011) - [c50]Eric S. Chung, James C. Hoe, Ken Mai:
CoRAM: an in-fabric memory architecture for FPGA-based computing. FPGA 2011: 97-106 - [c49]Michael Papamichael, James C. Hoe, Onur Mutlu:
FIST: A fast, lightweight, FPGA-friendly packet latency estimator for NoC modeling in full-system simulations. NOCS 2011: 137-144 - [c48]Eriko Nurvitadhi, James C. Hoe, Timothy Kam, Shih-Lien Lu:
Integrating formal verification and high-level processor pipeline synthesis. SASP 2011: 22-29 - 2010
- [j14]James C. Hoe, Doug Burger, Joel S. Emer, Derek Chiou, Resit Sendag, Joshua J. Yi:
The Future of Architectural Simulation. IEEE Micro 30(3): 8-18 (2010) - [j13]Eric S. Chung, James C. Hoe:
High-Level Design and Validation of the BlueSPARC Multithreaded Processor. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(10): 1459-1470 (2010) - [j12]Wei Yu, Tsuhan Chen, Franz Franchetti, James C. Hoe:
High Performance Stereo Vision Designed for Massively Data Parallel Platforms. IEEE Trans. Circuits Syst. Video Technol. 20(11): 1509-1519 (2010) - [c47]Eriko Nurvitadhi, James C. Hoe, Shih-Lien Lu, Timothy Kam:
Automatic multithreaded pipeline synthesis from transactional datapath specifications. DAC 2010: 314-319 - [c46]Eriko Nurvitadhi, James C. Hoe, Timothy Kam, Shih-Lien Lu:
Automatic pipelining from transactional datapath specifications. DATE 2010: 1001-1004 - [c45]Peter A. Milder, Franz Franchetti, James C. Hoe, Markus Püschel:
Hardware implementation of the discrete fourier transform with non-power-of-two problem size. ICASSP 2010: 1546-1549 - [c44]Wei Yu, Franz Franchetti, James C. Hoe, Yao-Jen Chang, Tsuhan Chen:
Fast bilateral filtering by adapting block size. ICIP 2010: 3281-3284 - [c43]Eric S. Chung, Peter A. Milder, James C. Hoe, Ken Mai:
Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs? MICRO 2010: 225-236 - [e1]James C. Hoe, Vikram S. Adve:
Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2010, Pittsburgh, Pennsylvania, USA, March 13-17, 2010. ACM 2010, ISBN 978-1-60558-839-1 [contents]
2000 – 2009
- 2009
- [j11]Markus Püschel, Peter A. Milder, James C. Hoe:
Permuting streaming data using RAMs. J. ACM 56(2): 10:1-10:34 (2009) - [j10]Eric S. Chung, Michael Papamichael, Eriko Nurvitadhi, James C. Hoe, Ken Mai, Babak Falsafi:
ProtoFlex: Towards Scalable, Full-System Multiprocessor Simulations Using FPGAs. ACM Trans. Reconfigurable Technol. Syst. 2(2): 15:1-15:32 (2009) - [c42]Shuichi Sakai, Hidetoshi Onodera, Hiroto Yasuura, James C. Hoe:
Dependable VLSI: device, design and architecture: how should they cooperate? ASP-DAC 2009: 859-860 - [c41]Peter A. Milder, James C. Hoe, Markus Püschel:
Automatic generation of streaming datapaths for arbitrary fixed permutations. DATE 2009: 1118-1123 - [c40]Wei Yu, Tsuhan Chen, James C. Hoe:
Real time stereo vision using exponential step cost aggregation on GPU. ICIP 2009: 4281-4284 - [c39]Forrest Brewer, James C. Hoe:
2009 MEMOCODE Co-Design Contest. MEMOCODE 2009: 66-68 - [c38]Eric S. Chung, James C. Hoe:
Implementing a high-performance multithreaded microprocessor: A case study in high-level design and validation. MEMOCODE 2009: 98-107 - [c37]Brian T. Gold, Babak Falsafi, James C. Hoe:
Chip-Level Redundancy in Distributed Shared-Memory Multiprocessors. PRDC 2009: 195-201 - 2008
- [j9]James C. Hoe, Jens Palsberg:
MEMOCODE 2006 guest editors' introduction. Des. Autom. Embed. Syst. 12(1-2): 95 (2008) - [c36]Peter A. Milder, Franz Franchetti, James C. Hoe, Markus Püschel:
Formal datapath representation and manipulation for implementing DSP transforms. DAC 2008: 385-390 - [c35]Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, Ken Mai:
A complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs. FPGA 2008: 77-86 - [c34]Franz Franchetti, Yevgen Voronenko, Peter A. Milder, Srinivas Chellappa, Marek R. Telgarsky, Hao Shen, Paolo D'Alberto, Frédéric de Mesmay, James C. Hoe, José M. F. Moura, Markus Püschel:
Domain-specific library generation for parallel software and hardware platforms. IPDPS 2008: 1-5 - [c33]Patrick Schaumont, Krste Asanovic, James C. Hoe:
MEMOCODE 2008 Co-Design Contest. MEMOCODE 2008: 151-154 - 2007
- [j8]John Wawrzynek, David A. Patterson, Mark Oskin, Shih-Lien Lu, Christoforos E. Kozyrakis, James C. Hoe, Derek Chiou, Krste Asanovic:
RAMP: Research Accelerator for Multiple Processors. IEEE Micro 27(2): 46-57 (2007) - [j7]Peter Tummeltshammer, James C. Hoe, Markus Püschel:
Time-Multiplexed Multiple-Constant Multiplication. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(9): 1551-1563 (2007) - [c32]Paolo D'Alberto, Peter A. Milder, Aliaksei Sandryhaila, Franz Franchetti, James C. Hoe, José M. F. Moura, Markus Püschel, Jeremy R. Johnson:
Generating FPGA-Accelerated DFT Libraries. FCCM 2007: 173-184 - [c31]Peter A. Milder, Franz Franchetti, James C. Hoe, Markus Püschel:
FFT Compiler: from math to efficient hardware HLDVT invited short paper. HLDVT 2007: 137-139 - [c30]Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi, Ken Mai:
PROToFLEX: FPGA-accelerated Hybrid Functional Simulator. IPDPS 2007: 1-6 - [c29]Forrest Brewer, James C. Hoe:
MEMOCODE 2007 Co-Design Contest. MEMOCODE 2007: 91-94 - [c28]Jangwoo Kim, Nikos Hardavellas, Ken Mai, Babak Falsafi, James C. Hoe:
Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding. MICRO 2007: 197-209 - [c27]Jangwoo Kim, Jared C. Smolens, Babak Falsafi, James C. Hoe:
PAI: A Lightweight Mechanism for Single-Node Memory Recovery in DSM Servers. PRDC 2007: 298-305 - 2006
- [j6]Thomas F. Wenisch, Roland E. Wunderlich, Michael Ferdman, Anastassia Ailamaki, Babak Falsafi, James C. Hoe:
SimFlex: Statistical Sampling of Computer System Simulation. IEEE Micro 26(4): 18-31 (2006) - [j5]Roland E. Wunderlich, Thomas F. Wenisch, Babak Falsafi, James C. Hoe:
Statistical sampling of microarchitecture simulation. ACM Trans. Model. Comput. Simul. 16(3): 197-224 (2006) - [c26]Peter A. Milder, Mohammad Ahmad, James C. Hoe, Markus Püschel:
Fast and accurate resource estimation of automatically generated custom DFT IP cores. FPGA 2006: 211-220 - [c25]David A. Patterson, Arvind, Krste Asanovic, Derek Chiou, James C. Hoe, Christos Kozyrakis, Shih-Lien Lu, Mark Oskin, Jan M. Rabaey, John Wawrzynek:
Research accelerator for multiple processors. Hot Chips Symposium 2006: 1-42 - [c24]Marek R. Telgarsky, James C. Hoe, José M. F. Moura:
Spiral: Joint Runtime and Energy Optimization of Linear Transforms. ICASSP (3) 2006: 1048-1051 - [c23]Thomas F. Wenisch, Roland E. Wunderlich, Babak Falsafi, James C. Hoe:
Statistical sampling of microarchitecture simulation. IPDPS 2006 - [c22]Thomas F. Wenisch, Roland E. Wunderlich, Babak Falsafi, James C. Hoe:
Simulation sampling with live-points. ISPASS 2006: 2-12 - [c21]Jared C. Smolens, Brian T. Gold, Babak Falsafi, James C. Hoe:
Reunion: Complexity-Effective Multicore Redundancy. MICRO 2006: 223-234 - 2005
- [j4]Brian T. Gold, Jangwoo Kim, Jared C. Smolens, Eric S. Chung, Vasileios Liaskovitis, Eriko Nurvitadhi, Babak Falsafi, James C. Hoe, Andreas Nowatzyk:
TRUSS: A Reliable, Scalable Server Architecture. IEEE Micro 25(6): 51-59 (2005) - [c20]Grace Nordin, Peter A. Milder, James C. Hoe, Markus Püschel:
Automatic generation of customized discrete fourier transform IPs. DAC 2005: 471-474 - [c19]Thomas F. Wenisch, Roland E. Wunderlich, Babak Falsafi, James C. Hoe:
TurboSMARTS: accurate microarchitecture simulation sampling in minutes. SIGMETRICS 2005: 408-409 - 2004
- [j3]Jared C. Smolens, Brian T. Gold, Jangwoo Kim, Babak Falsafi, James C. Hoe, Andreas Nowatzyk:
Fingerprinting: Bounding Soft-Error-Detection Latency and Bandwidth. IEEE Micro 24(6): 22-29 (2004) - [j2]Nikolaos Hardavellas, Stephen Somogyi, Thomas F. Wenisch, Roland E. Wunderlich, Shelley Chen, Jangwoo Kim, Babak Falsafi, James C. Hoe, Andreas Nowatzyk:
SimFlex: a fast, accurate, flexible full-system simulation framework for performance evaluation of server architecture. SIGMETRICS Perform. Evaluation Rev. 31(4): 31-34 (2004) - [j1]James C. Hoe, Arvind:
Operation-centric hardware description and synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(9): 1277-1288 (2004) - [c18]Jared C. Smolens, Brian T. Gold, Jangwoo Kim, Babak Falsafi, James C. Hoe, Andreas Nowatzyk:
Fingerprinting: bounding soft-error detection latency and bandwidth. ASPLOS 2004: 224-234 - [c17]Peter Tummeltshammer, James C. Hoe, Markus Püschel:
Multiple constant multiplication by time-multiplexed mapping of addition chains. DAC 2004: 826-829 - [c16]Roland E. Wunderlich, James C. Hoe:
In-system FPGA prototyping of an itanium microarchitecture. FPGA 2004: 255 - [c15]Adam C. Zelinski, Markus Püschel, Smarahara Misra, James C. Hoe:
Automatic cost minimization for multiplierless implementations of discrete signal transforms. ICASSP (5) 2004: 221-224 - [c14]Markus Püschel, Adam C. Zelinski, James C. Hoe:
Custom-optimized multiplierless implementations of DSP algorithms. ICCAD 2004: 175-182 - [c13]Roland E. Wunderlich, James C. Hoe:
In-System FPGA Prototyping of an Itanium Microarchitecture. ICCD 2004: 288-294 - [c12]Grace Nordin, James C. Hoe:
Synchronous extensions to operation centric hardware description languages. MEMOCODE 2004: 49-56 - [c11]Jared C. Smolens, Jangwoo Kim, James C. Hoe, Babak Falsafi:
Efficient Resource Sharing in Concurrent Error Detecting Superscalar Microarchitectures. MICRO 2004: 257-268 - 2003
- [c10]Joydeep Ray, James C. Hoe:
High-level modeling and FPGA prototyping of microprocessors. FPGA 2003: 100-107 - [c9]Roland E. Wunderlich, Thomas F. Wenisch, Babak Falsafi, James C. Hoe:
SMARTS: Accelerating Microarchitecture Simulation via Rigorous Statistical Sampling. ISCA 2003: 84-95 - [c8]James C. Hoe:
Superscalar out-of-order demystified in four instructions. WCAE 2003: 5 - 2001
- [c7]Joydeep Ray, James C. Hoe, Babak Falsafi:
Dual use of superscalar datapath for transient-fault detection and recovery. MICRO 2001: 214-224 - 2000
- [b1]James C. Hoe:
Operation-centric hardware description and synthesis. Massachusetts Institute of Technology, Cambridge, MA, USA, 2000 - [c6]James C. Hoe, Arvind:
Synthesis of Operation-Centric Hardware Descriptions. ICCAD 2000: 511-518
1990 – 1999
- 1999
- [c5]James C. Hoe, Arvind:
Hardware Synthesis from Term Rewriting Systems. VLSI 1999: 595-619 - [c4]James C. Hoe, Chris Hill, Alistair Adcroft:
A Personal Supercomputer for Climate Research. SC 1999: 59 - 1998
- [c3]