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Ching-Long Su
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2010 – 2019
- 2011
- [j2]Ching-Long Su, S. M. Yang, W. L. Huang:
A two-stage algorithm integrating genetic algorithm and modified Newton method for neural network training in engineering systems. Expert Syst. Appl. 38(10): 12189-12194 (2011)
2000 – 2009
- 2000
- [c10]Ching-Long Su, Chein-Wei Jen:
Motion estimation using on-line arithmetic. ISCAS 2000: 683-686
1990 – 1999
- 1996
- [c9]Ching-Long Su, Yin-Tsung Hwang:
Distributed arithmetic-based architectures for high speed IIR filter design. ICPADS 1996: 156-161 - 1995
- [c8]Ching-Long Su, Alvin M. Despain:
Cache designs for energy efficiency. HICSS (1) 1995: 306-315 - [c7]Ching-Long Su, Alvin M. Despain:
Cache design trade-offs for power and performance optimization: a case study. ISLPD 1995: 63-68 - 1994
- [j1]Ching-Long Su, Chi-Ying Tsui, Alvin M. Despain:
Saving Power in the Control Path of Embedded Processors. IEEE Des. Test Comput. 11(4): 24-30 (1994) - [c6]Ching-Long Su, Chi-Ying Tsui, Alvin M. Despain:
Lower Power Architecture Design and Compilation Techniques for High-Performance Processors. COMPCON 1994: 489-498 - [c5]Ching-Long Su, Alvin M. Despain:
Hardware-software co-designing benchmark-driven superpipelined instruction set processors. COMPSAC 1994 - [c4]Ching-Long Su, Chin-Chi Teng, Alvin M. Despain:
A Study of Cache Hashing Functions for Symbolic Applications in Micro-Parallel Processors. ICPADS 1994: 530-537 - [c3]Ching-Long Su, Alvin M. Despain:
Branch with Masked Squashing in Superpipelined Processors. ISCA 1994: 130-140 - [c2]Ching-Long Su, Alvin M. Despain:
Minimizing branch misprediction penalties for superpipelined processors. MICRO 1994: 138-142 - 1992
- [c1]Iksoo Pyo, Ching-Long Su, Ing-Jer Huang, Kuo-Rueih Pan, Yong-Seon Koh, Chi-Ying Tsui, Hsu-Tsun Chen, Gino Cheng, Shihming Liu, Shiqun Wu, Alvin M. Despain:
Application-Driven Design Automation for Microprocessor Design. DAC 1992: 512-517
Coauthor Index
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