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2020 – today
- 2022
[c9]Subrata Das
, Debesh Kumar Das, Soumya Pandit:
Reliability Aware Global Routing of Graphene Nanoribbon Based Interconnect. VDAT 2022: 373-386- 2021
- [c8]Subrata Das, Petr Fiser, Soumya Pandit, Debesh Kumar Das:
Minimization of Switching Activity of Graphene Based Circuits. VLSID 2021: 139-144 - 2020
- [j5]Subrata Das, Debesh Kumar Das, Soumya Pandit:
A Global Routing Method for Graphene Nanoribbons Based Circuits and Interconnects. ACM J. Emerg. Technol. Comput. Syst. 16(3): 31:1-31:28 (2020)
2010 – 2019
- 2019
- [c7]Samik Basu, Soumya Pandit, Amlan Chakrabarti, Soma Barman Mandal:
FPGA Based Hardware Design for Noise Suppression and Seismic Event Detection. iSES 2019: 382-385 - 2014
- [c6]Debayan Bairagi, Soumya Pandit:
Study of reverse substrate bias effect of 22nm node epitaxial delta doped channel MOS transistor for low power SoC applications. VDAT 2014: 1-6 - 2013
- [c5]Somnath Paul, Abhijit Dana, Soumya Pandit:
An Improved g m /I D Methodology for Ultra-Low-Power Nano-Scale CMOS OTA Design. VDAT 2013: 128-137 - 2012
- [j4]Joyjit Mukhopadhyay, Soumya Pandit:
Modeling and Design of a Nano Scale CMOS Inverter for Symmetric Switching Characteristics. VLSI Design 2012: 505983:1-505983:13 (2012) - 2011
- [j3]Soumya Pandit, Chittaranjan A. Mandal, Amit Patra:
A Methodology for Generation of Performance Models for the Sizing of Analog High-Level Topologies. VLSI Design 2011: 475952:1-475952:17 (2011) - [c4]Sipra Mandal, Soumya Pandit:
Statistical Simulation and Modeling of Nano-scale CMOS VCO Using Artificial Neural Network. VLSI Design 2011: 94-99 - 2010
- [j2]Soumya Pandit, Chittaranjan A. Mandal, Amit Patra:
An automated high-level topology generation procedure for continuous-time SigmaDelta modulator. Integr. 43(3): 289-304 (2010)
2000 – 2009
- 2009
- [c3]Soumya Pandit, Chittaranjan A. Mandal, Amit Patra:
Systematic Methodology for High-Level Performance Modeling of Analog Systems. VLSI Design 2009: 361-366 - 2008
- [j1]Soumya Pandit, Sumit K. Bhattacharya, Chittaranjan A. Mandal, Amit Patra:
A Fast Exploration Procedure for Analog High-Level Specification Translation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(8): 1493-1497 (2008) - 2006
- [c2]Soumya Pandit, Sougata Kar, Chittaranjan A. Mandal, Amit Patra:
High level synthesis of higher order continuous time state variable filters with minimum sensitivity and hardware count. DATE 2006: 1203-1204 - [c1]Soumya Pandit, Chittaranjan A. Mandal, Amit Patra:
A formal approach for high level synthesis of linear analog systems. ACM Great Lakes Symposium on VLSI 2006: 345-348
Coauthor Index
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