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Jan Butas
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2000 – 2009
- 2001
- [j2]Jan Butas, Chiu-Sing Choy, Juraj Povazanec, Cheong-Fat Chan:
Asynchronous cross-pipelined multiplier. IEEE J. Solid State Circuits 36(8): 1272-1275 (2001) - [j1]Oliver Chiu-sing Choy, Jan Butas, Juraj Povazanec, Cheong-Fat Chan:
A New Control Circuit for Asynchronous Micropipelines. IEEE Trans. Computers 50(9): 992-997 (2001) - [c4]Pui-Lam Siu, Chiu-sing Choy, Jan Butas, Cheong-Fat Chan:
A low power asynchronous DES. ISCAS (4) 2001: 538-541 - [c3]Chi-Wai Lee, Chiu-sing Choy, Jan Butas, Cheong-Fat Chan:
A pipelined dataflow small micro-coded asynchronous processor and its application to DCT. ISCAS (4) 2001: 910-913 - 2000
- [c2]Tin-Yau Tang, Chiu-sing Choy, Jan Butas, Cheong-Fat Chan:
An ALU design using a novel asynchronous pipeline architecture. ISCAS 2000: 361-364
1990 – 1999
- 1999
- [c1]Juraj Povazanec, Oliver Chiu-sing Choy, Cheong-Fat Chan, Jan Butas, Yeu-qiu Zhang, Jing-Ling Yang, Tin-yan Tang:
Pipelined Dataflow Architecture of a Small Processor. PDPTA 1999: 1217-1223
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