Inter-chip Clock Network Synthesis on Passive Interposer of 2.5D Chiplet Considering Transmission Line Effect.

Wed, 01 Jan 2025 00:00:00 +0100

Tai Yan, Yiyu Wang, Zhan Li, Ning Xu, Yuanqing Cheng:
Inter-chip Clock Network Synthesis on Passive Interposer of 2.5D Chiplet Considering Transmission Line Effect. VLSI-SoC 2025: 1-5