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ORCIDTomonori Sekiguchi
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2020 – today
- 2024
[i1]Naoto Sato, Tomonori Sekiguchi, Takeru Utsugi, Hiroyuki Mizuno:
Generating Shuttling Procedures for Constrained Silicon Quantum Dot Array. CoRR abs/2401.14683 (2024)- 2020
- [j13]Yuki Furubayashi
, Takashi Oshima, Taizo Yamawaki, Keiki Watanabe, Keijiro Mori, Naoki Mori, Akira Matsumoto, Yudai Kamada, Atsushi Isobe, Tomonori Sekiguchi:
A 22-ng/ $\surd$ Hz 17-mW Capacitive MEMS Accelerometer With Electrically Separated Mass Structure and Digital Noise- Reduction Techniques. IEEE J. Solid State Circuits 55(9): 2539-2552 (2020)
2010 – 2019
- 2019
- [c7]Yuki Furubayashi, Takashi Oshima, Taizo Yamawaki, Keiki Watanabe, Keijiro Mori, Naoki Mori, Akira Matsumoto, Hideto Kazama, Yudai Kamada, Atsushi Isobe, Tomonori Sekiguchi:
A 22ng/√Hz 17mW MEMS Accelerometer with Digital Noise-Reduction Techniques. ISSCC 2019: 182-184 - 2018
- [c6]Atsushi Isobe, Yudai Kamada, Takashi Oshima, Yuki Furubayashi, Noriyuki Sakuma, Chisaki Takubo, Yasushi Tainaka, Keiki Watanabe, Tomonori Sekiguchi:
Design of Perforated Membrane for Low-Noise Capacitive MEMS Accelerometers. IEEE SENSORS 2018: 1-4 - 2016
- [c5]Joan Giner, Yuhua Zhang, Takashi Shiota, Daisuke Maeda, Kazuo Ono, Shinya Kajiyama, Takashi Oshima, Taizo Yamawaki, Tomonori Sekiguchi:
A concentrated springs architecture for single-digit frequency symmetry in Si MEMS gyroscope. IEEE SENSORS 2016: 1-3 - [c4]Kazuo Ono, Daisuke Maeda, Takashi Oshima, Toshiaki Nakamura, Joan Giner, Tomonori Sekiguchi:
A low 1/f-noise accelerometer frontend using chopper stabilization at a frequency matched with a notch of quantization noise. IEEE SENSORS 2016: 1-3 - 2012
- [j12]Akira Kotabe, Riichiro Takemura, Yoshimitsu Yanagawa, Tomonori Sekiguchi, Kiyoo Itoh:
Small-Sized Leakage-Controlled Gated Sense Amplifier for 0.5-V Multi-Gigabit DRAM Arrays. IEICE Trans. Electron. 95-C(4): 594-599 (2012) - [j11]Satoru Akiyama, Riichiro Takemura, Tomonori Sekiguchi, Akira Kotabe, Kiyoo Itoh:
A Low-Vt Small-Offset Gated-Preamplifier for Sub-1-V DRAM Mid-Point Sensing. IEICE Trans. Electron. 95-C(4): 600-608 (2012) - 2011
- [j10]Tomonori Sekiguchi, Kazuo Ono, Akira Kotabe, Yoshimitsu Yanagawa:
1-Tbyte/s 1-Gbit DRAM Architecture Using 3-D Interconnect for High-Throughput Computing. IEEE J. Solid State Circuits 46(4): 828-837 (2011) - 2010
- [j9]Akira Kotabe, Yoshimitsu Yanagawa, Satoru Akiyama, Tomonori Sekiguchi:
0.5-V Low- V T CMOS Preamplifier for Low-Power and High-Speed Gigabit-DRAM Arrays. IEEE J. Solid State Circuits 45(11): 2348-2355 (2010)
2000 – 2009
- 2009
- [c3]Satoru Akiyama, Tomonori Sekiguchi, Riichiro Takemura, Akira Kotabe, Kiyoo Itoh:
Low-Vt small-offset gated preamplifier for sub-1V gigabit DRAM arrays. ISSCC 2009: 142-143 - 2008
- [j8]Kiyoo Itoh, Hideaki Kurata, Kenichi Osada, Tomonori Sekiguchi:
Memory at VLSI Circuits Symposium. IEEE J. Solid State Circuits 43(4): 762-768 (2008) - 2007
- [j7]Riichiro Takemura, Kiyoo Itoh, Tomonori Sekiguchi, Satoru Akiyama, Satoru Hanzawa, Kazuhiko Kajigaya, Takayuki Kawahara:
Long-Retention-Time, High-Speed DRAM Array with 12-F2 Twin Cell for Sub 1-V Operation. IEICE Trans. Electron. 90-C(4): 758-764 (2007) - 2006
- [j6]Satoru Akiyama, Tomonori Sekiguchi, Kazuhiko Kajigaya, Satoru Hanzawa, Riichiro Takemura, Takayuki Kawahara:
Concordant memory design: an integrated statistical design approach for multi-gigabit DRAM. IEEE J. Solid State Circuits 41(1): 107-112 (2006) - [c2]Riichiro Takemura, Kiyoo Itoh, Tomonori Sekiguchi:
A 0.5-V FD-SOI twin-cell DRAM with offset-free dynamic-VT sense amplifiers. ISLPED 2006: 123-126 - 2005
- [c1]Satoru Hanzawa, Takeshi Sakata, Kazuhiko Kajigaya, Riichiro Takemura, Tomonori Sekiguchi, Takayuki Kawahara:
A ternary/quaternary CAM architecture with an NPU-side IP-address compression scheme and a dynamic re-configurable CODEC scheme for large-scale flow-table lookup. ICC 2005: 1048-1052 - 2002
- [j5]Tomonori Sekiguchi, Kiyoo Itoh, Tsugio Takahashi, Masahiro Sugaya, Hiroki Fujisawa, Masayuki Nakamura, Kazuhiko Kajigaya, Katsutaka Kimura:
A low-impedance open-bitline array for multigigabit DRAM. IEEE J. Solid State Circuits 37(4): 487-498 (2002) - 2001
- [j4]Tsugio Takahashi, Tomonori Sekiguchi, Riichiro Takemura, Seiji Narui, Hiroki Fujisawa, Shinichi Miyatake, Makoto Morino, Koji Arai, Satoru Yamada, Shoji Shukuri, Masayuki Nakamura, Yoshitaka Tadaki, Kazuhiko Kajigaya, Katsutaka Kimura, Kiyoo Itoh:
A multigigabit DRAM technology with 6F2 open-bitline cell, distributed overdriven sensing, and stacked-flash fuse. IEEE J. Solid State Circuits 36(11): 1721-1727 (2001)
1990 – 1999
- 1997
- [j3]Hiroki Fujisawa, Takeshi Sakata, Tomonori Sekiguchi, Osamu Nagashima, Katsutaka Kimura, Kazuhiko Kajigaya:
The charge-share modified (CSM) precharge-level architecture for high-speed and low-power ferroelectric memory. IEEE J. Solid State Circuits 32(5): 655-661 (1997) - 1995
- [j2]Takeshi Sakata, Masashi Horiguchi, Tomonori Sekiguchi, Shigeki Ueda, Hitoshi Tanaka, Eiji Yamasaki, Yoshinobu Nakagome, Masakazu Aoki, Toru Kaga, Makoto Ohkura, Ryo Nagai, Fumio Murai, Toshihiko Tanaka, Shimpei Iijima, Natsuki Yokoyama, Yasushi Gotoh, Ken'ichi Shoji, Teruaki Kisu, Hisaomi Yamashita, Takashi Nishida, Eiji Takeda:
An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture. IEEE J. Solid State Circuits 30(11): 1165-1173 (1995) - [j1]Tomonori Sekiguchi, Masashi Horiguchi, Takeshi Sakata, Yoshinobu Nakagome, Shigeki Ueda, Masakazu Aoki:
Low-noise, high-speed data transmission using a ringing-canceling output buffer. IEEE J. Solid State Circuits 30(12): 1569-1574 (1995)
Coauthor Index
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