A 2nm Clock-Edge Architecture for Processor Clock-Power Reduction.

Thu, 01 Jan 2026 00:00:00 +0100

Yimai Peng, Daniel Yingling, Basma Hajri, Robert Vachon, Fikre Tsigabu Gebreyohannes, Vincent Li, Ghanshyam Chhetri, Keith A. Bowman:
A 2nm Clock-Edge Architecture for Processor Clock-Power Reduction. ISSCC 2026: 172-174