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Breeta SenGupta
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2010 – 2019
- 2019
- [j3]Breeta SenGupta, Dimitar Nikolov, Assmitra Dash, Erik Larsson
:
Test Flow Selection for Stacked Integrated Circuits. J. Electron. Test. 35(4): 425-440 (2019) - 2017
- [j2]Breeta SenGupta, Dimitar Nikolov, Urban Ingelsson, Erik Larsson
:
Test Planning for Core-based Integrated Circuits under Power Constraints. J. Electron. Test. 33(1): 7-23 (2017) - 2014
- [c3]Breeta SenGupta, Erik Larsson
:
Test planning and test access mechanism design for stacked chips using ILP. VTS 2014: 1-6 - 2012
- [j1]Breeta SenGupta, Urban Ingelsson, Erik Larsson
:
Scheduling Tests for 3D Stacked Chips under Power Constraints. J. Electron. Test. 28(1): 121-135 (2012) - [c2]Breeta SenGupta, Urban Ingelsson, Erik Larsson
:
Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias. VLSI Design 2012: 442-447 - 2011
- [c1]Breeta SenGupta, Urban Ingelsson, Erik Larsson
:
Scheduling Tests for 3D Stacked Chips under Power Constraints. DELTA 2011: 72-77
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