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ORCIDMarc-André Daigneault
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2010 – 2019
- 2018
[j3]Marc-André Daigneault, Jean-Pierre David:
Automated Synthesis of Streaming Transfer Level Hardware Designs. ACM Trans. Reconfigurable Technol. Syst. 11(2): 13:1-13:22 (2018)- 2015
- [c7]Marc-André Daigneault, Jean-Pierre David:
Intermediate-Level Synthesis of a Gauss-Jordan Elimination Linear Solver. IPDPS Workshops 2015: 176-181 - 2014
- [j2]Marc-André Daigneault, Jean-Pierre David:
Fast description and synthesis of control-dominant circuits. Comput. Electr. Eng. 40(4): 1199-1214 (2014) - 2013
- [c6]Marc-André Daigneault, Jean-Pierre David:
High-Level Description and Synthesis of Floating-Point Accumulators on FPGA. FCCM 2013: 206-209 - [c5]Marc-André Daigneault, Jean-Pierre David:
Hardware description and synthesis of control-intensive reconfigurable dataflow architectures (abstract only). FPGA 2013: 274-275 - 2012
- [c4]Marc-André Daigneault, Jean-Pierre David:
Raising the abstraction level of HDL for control-dominant applications. FPL 2012: 515-518 - [c3]Marc-André Daigneault, Jean-Pierre David:
Synchronized-transfer-level design methodology applied to hardware matrix multiplication. ReConFig 2012: 1-7 - 2011
- [j1]Marc-André Daigneault, Jean-Pierre David:
A High-Resolution Time-to-Digital Converter on FPGA Using Dynamic Reconfiguration. IEEE Trans. Instrum. Meas. 60(6): 2070-2079 (2011) - 2010
- [c2]Marc-André Daigneault, Jean-Pierre David:
Towards 5ps resolution TDC on a dynamically reconfigurable FPGA (abstract only). FPGA 2010: 283
2000 – 2009
- 2008
- [c1]Marc-André Daigneault, J. M. Pierre Langlois, Jean-Pierre David:
Application Specific Instruction set processor specialized for block motion estimation. ICCD 2008: 266-271
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