BibTeX records: Yen-Huei Chen

download as .bib file

@article{DBLP:journals/jssc/ChangCCCWLFLLWY21,
  author    = {Tsung{-}Yung Jonathan Chang and
               Yen{-}Huei Chen and
               Wei{-}Min Chan and
               Hank Cheng and
               Po{-}Sheng Wang and
               Yangsyu Lin and
               Hidehiro Fujiwara and
               Robin Lee and
               Hung{-}Jen Liao and
               Ping{-}Wei Wang and
               Geoffrey Yeap and
               Quincy Li},
  title     = {A 5-nm 135-Mb {SRAM} in {EUV} and High-Mobility Channel FinFET Technology
               With Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes
               for High-Density and Low-V\({}_{\mbox{MIN}}\) Applications},
  journal   = {{IEEE} J. Solid State Circuits},
  volume    = {56},
  number    = {1},
  pages     = {179--187},
  year      = {2021},
  url       = {https://doi.org/10.1109/JSSC.2020.3034241},
  doi       = {10.1109/JSSC.2020.3034241},
  timestamp = {Sat, 09 Jan 2021 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/journals/jssc/ChangCCCWLFLLWY21.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ChangCCCWLFLLWY20,
  author    = {Jonathan Chang and
               Yen{-}Huei Chen and
               Gary Chan and
               Hank Cheng and
               Po{-}Sheng Wang and
               Yangsyu Lin and
               Hidehiro Fujiwara and
               Robin Lee and
               Hung{-}Jen Liao and
               Ping{-}Wei Wang and
               Geoffrey Yeap and
               Quincy Li},
  title     = {15.1 {A} 5nm 135Mb {SRAM} in {EUV} and High-Mobility-Channel FinFET
               Technology with Metal Coupling and Charge-Sharing Write-Assist Circuitry
               Schemes for High-Density and Low-VMIN Applications},
  booktitle = {2020 {IEEE} International Solid- State Circuits Conference, {ISSCC}
               2020, San Francisco, CA, USA, February 16-20, 2020},
  pages     = {238--240},
  publisher = {{IEEE}},
  year      = {2020},
  url       = {https://doi.org/10.1109/ISSCC19947.2020.9062967},
  doi       = {10.1109/ISSCC19947.2020.9062967},
  timestamp = {Sat, 18 Apr 2020 17:41:44 +0200},
  biburl    = {https://dblp.org/rec/conf/isscc/ChangCCCWLFLLWY20.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/FujiwaraLPLHLLC19,
  author    = {Hidehiro Fujiwara and
               Chih{-}Yu Lin and
               Hsien{-}Yu Pan and
               Cheng{-}Han Lin and
               Po{-}Yi Huang and
               Kao{-}Cheng Lin and
               Jhon{-}Jhy Liaw and
               Yen{-}Huei Chen and
               Hung{-}Jen Liao and
               Jonathan Chang},
  title     = {A 7nm 2.1GHz Dual-Port {SRAM} with {WL-RC} Optimization and Dummy-Read-Recovery
               Circuitry to Mitigate Read- Disturb-Write Issue},
  booktitle = {{IEEE} International Solid- State Circuits Conference, {ISSCC} 2019,
               San Francisco, CA, USA, February 17-21, 2019},
  pages     = {390--392},
  publisher = {{IEEE}},
  year      = {2019},
  url       = {https://doi.org/10.1109/ISSCC.2019.8662415},
  doi       = {10.1109/ISSCC.2019.8662415},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/isscc/FujiwaraLPLHLLC19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ChangCCSCFLLHLL17,
  author    = {Jonathan Chang and
               Yen{-}Huei Chen and
               Wei{-}Min Chan and
               Sahil Preet Singh and
               Hank Cheng and
               Hidehiro Fujiwara and
               Jih{-}Yu Lin and
               Kao{-}Cheng Lin and
               John Hung and
               Robin Lee and
               Hung{-}Jen Liao and
               Jhon{-}Jhy Liaw and
               Quincy Li and
               Chih{-}Yung Lin and
               Mu{-}Chi Chiang and
               Shien{-}Yang Wu},
  title     = {12.1 {A} 7nm 256Mb {SRAM} in high-k metal-gate FinFET technology with
               write-assist circuitry for low-VMIN applications},
  booktitle = {2017 {IEEE} International Solid-State Circuits Conference, {ISSCC}
               2017, San Francisco, CA, USA, February 5-9, 2017},
  pages     = {206--207},
  publisher = {{IEEE}},
  year      = {2017},
  url       = {https://doi.org/10.1109/ISSCC.2017.7870333},
  doi       = {10.1109/ISSCC.2017.7870333},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/isscc/ChangCCSCFLLHLL17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asscc/FujiwaraCLWSWLC16,
  author    = {Hidehiro Fujiwara and
               Yen{-}Huei Chen and
               Chih{-}Yu Lin and
               Wei{-}Cheng Wu and
               Dar Sun and
               Shin{-}Rung Wu and
               Hung{-}Jen Liao and
               Jonathan Chang},
  title     = {A 64-Kb 0.37V 28nm 10T-SRAM with mixed-Vth read-port and boosted {WL}
               scheme for IoT applications},
  booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2016, Toyama,
               Japan, November 7-9, 2016},
  pages     = {185--188},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/ASSCC.2016.7844166},
  doi       = {10.1109/ASSCC.2016.7844166},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/asscc/FujiwaraCLWSWLC16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ChenLWCLLC16,
  author    = {Yen{-}Huei Chen and
               Kao{-}Cheng Lin and
               Ching{-}Wei Wu and
               Wei{-}Min Chan and
               Jhon{-}Jhy Liaw and
               Hung{-}Jen Liao and
               Jonathan Chang},
  title     = {A 16nm dual-port {SRAM} with partial suppressed word-line, dummy read
               recovery and negative bit-line circuitries for low {VMIN} applications},
  booktitle = {2016 {IEEE} Symposium on {VLSI} Circuits, {VLSIC} 2016, Honolulu,
               HI, USA, June 15-17, 2016},
  pages     = {1--2},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {https://doi.org/10.1109/VLSIC.2016.7573459},
  doi       = {10.1109/VLSIC.2016.7573459},
  timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl    = {https://dblp.org/rec/conf/vlsic/ChenLWCLLC16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ChenCWLPLCLLCWC15,
  author    = {Yen{-}Huei Chen and
               Wei{-}Min Chan and
               Wei{-}Cheng Wu and
               Hung{-}Jen Liao and
               Kuo{-}Hua Pan and
               Jhon{-}Jhy Liaw and
               Tang{-}Hsuan Chung and
               Quincy Li and
               Chih{-}Yung Lin and
               Mu{-}Chi Chiang and
               Shien{-}Yang Wu and
               Jonathan Chang},
  title     = {A 16 nm 128 Mb {SRAM} in High-{\(\kappa\)} Metal-Gate FinFET Technology
               With Write-Assist Circuitry for Low-VMIN Applications},
  journal   = {{IEEE} J. Solid State Circuits},
  volume    = {50},
  number    = {1},
  pages     = {170--177},
  year      = {2015},
  url       = {https://doi.org/10.1109/JSSC.2014.2349977},
  doi       = {10.1109/JSSC.2014.2349977},
  timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/jssc/ChenCWLPLCLLCWC15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/FujiwaraWCLSWLL15,
  author    = {Hidehiro Fujiwara and
               Li{-}Wen Wang and
               Yen{-}Huei Chen and
               Kao{-}Cheng Lin and
               Dar Sun and
               Shin{-}Rung Wu and
               Jhon{-}Jhy Liaw and
               Chih{-}Yung Lin and
               Mu{-}Chi Chiang and
               Hung{-}Jen Liao and
               Shien{-}Yang Wu and
               Jonathan Chang},
  title     = {17.2 {A} 64kb 16nm asynchronous disturb current free 2-port {SRAM}
               with {PMOS} pass-gates for FinFET technologies},
  booktitle = {2015 {IEEE} International Solid-State Circuits Conference, {ISSCC}
               2015, Digest of Technical Papers, San Francisco, CA, USA, February
               22-26, 2015},
  pages     = {1--3},
  publisher = {{IEEE}},
  year      = {2015},
  url       = {https://doi.org/10.1109/ISSCC.2015.7063051},
  doi       = {10.1109/ISSCC.2015.7063051},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/isscc/FujiwaraWCLSWLL15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ChenCWLPLCLCLCW14,
  author    = {Yen{-}Huei Chen and
               Wei{-}Min Chan and
               Wei{-}Cheng Wu and
               Hung{-}Jen Liao and
               Kuo{-}Hua Pan and
               Jhon{-}Jhy Liaw and
               Tang{-}Hsuan Chung and
               Quincy Li and
               George H. Chang and
               Chih{-}Yung Lin and
               Mu{-}Chi Chiang and
               Shien{-}Yang Wu and
               Sreedhar Natarajan and
               Jonathan Chang},
  title     = {13.5 {A} 16nm 128Mb {SRAM} in high-{\(\kappa\)} metal-gate FinFET
               technology with write-assist circuitry for low-VMIN applications},
  booktitle = {2014 {IEEE} International Conference on Solid-State Circuits Conference,
               {ISSCC} 2014, Digest of Technical Papers, San Francisco, CA, USA,
               February 9-13, 2014},
  pages     = {238--239},
  publisher = {{IEEE}},
  year      = {2014},
  url       = {https://doi.org/10.1109/ISSCC.2014.6757416},
  doi       = {10.1109/ISSCC.2014.6757416},
  timestamp = {Mon, 10 Aug 2020 16:35:20 +0200},
  biburl    = {https://dblp.org/rec/conf/isscc/ChenCWLPLCLCLCW14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ChangCCCLLCNLWLWCCC13,
  author    = {Jonathan Chang and
               Yen{-}Huei Chen and
               Hank Cheng and
               Wei{-}Min Chan and
               Hung{-}Jen Liao and
               Quincy Li and
               Stanley Chang and
               Sreedhar Natarajan and
               Robin Lee and
               Ping{-}Wei Wang and
               Shyue{-}Shyh Lin and
               Chung{-}Cheng Wu and
               Kuan{-}Lun Cheng and
               Min Cao and
               George H. Chang},
  title     = {A 20nm 112Mb {SRAM} in High-{\cyrchar\cyrk} metal-gate with assist
               circuitry for low-leakage and low-VMIN applications},
  booktitle = {2013 {IEEE} International Solid-State Circuits Conference - Digest
               of Technical Papers, {ISSCC} 2013, San Francisco, CA, USA, February
               17-21, 2013},
  pages     = {316--317},
  publisher = {{IEEE}},
  year      = {2013},
  url       = {https://doi.org/10.1109/ISSCC.2013.6487750},
  doi       = {10.1109/ISSCC.2013.6487750},
  timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl    = {https://dblp.org/rec/conf/isscc/ChangCCCLLCNLWLWCCC13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ChenCLCSLWCY12,
  author    = {Yen{-}Huei Chen and
               Shao{-}Yu Chou and
               Quincy Li and
               Wei{-}Min Chan and
               Dar Sun and
               Hung{-}Jen Liao and
               Ping Wang and
               Meng{-}Fan Chang and
               Hiroyuki Yamauchi},
  title     = {Compact Measurement Schemes for Bit-Line Swing, Sense Amplifier Offset
               Voltage, and Word-Line Pulse Width to Characterize Sensing Tolerance
               Margin in a 40 nm Fully Functional Embedded {SRAM}},
  journal   = {{IEEE} J. Solid State Circuits},
  volume    = {47},
  number    = {4},
  pages     = {969--980},
  year      = {2012},
  url       = {https://doi.org/10.1109/JSSC.2012.2185180},
  doi       = {10.1109/JSSC.2012.2185180},
  timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/jssc/ChenCLCSLWCY12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ChenCCPWLLY09,
  author    = {Yen{-}Huei Chen and
               Gary Chan and
               Shao{-}Yu Chou and
               Hsien{-}Yu Pan and
               Jui{-}Jen Wu and
               Robin Lee and
               Hung{-}Jen Liao and
               Hiroyuki Yamauchi},
  title     = {A 0.6 {V} Dual-Rail Compiler {SRAM} Design on 45 nm {CMOS} Technology
               With Adaptive {SRAM} Power for Lower VDD{\_}min VLSIs},
  journal   = {{IEEE} J. Solid State Circuits},
  volume    = {44},
  number    = {4},
  pages     = {1209--1215},
  year      = {2009},
  url       = {https://doi.org/10.1109/JSSC.2009.2014208},
  doi       = {10.1109/JSSC.2009.2014208},
  timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/jssc/ChenCCPWLLY09.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
a service of Schloss Dagstuhl - Leibniz Center for Informatics