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2000 – 2009
- 2004
[c8]Andrés Takach, Simon Waters, Peter Gutberlet:
Fast Bit-Accurate C++ Datatypes For Functional System Verification and Synthesis. FDL 2004: 337-345
1990 – 1999
- 1997
- [b1]Peter Gutberlet:
Spezifikation und Synthese aus taktfreien VHDL Verhaltensbeschreibungen. Eberhard Karls University of Tübingen, 1997, pp. 1-185 - 1996
- [c7]Xun Xiong, Peter Gutberlet, Wolfgang Rosenstiel:
Automatic generation of interprocess communication in the PARAGON system. RSP 1996: 24-29 - 1994
- [c6]Peter Gutberlet, Wolfgang Rosenstiel:
Timing preserving interface transformations for the synthesis of behavioral VHDL. EURO-DAC 1994: 618-623 - [c5]Peter Gutberlet, Wolfgang Rosenstiel:
Specification of interface components for synchronous data paths. HLSS 1994: 134-139 - 1993
- [c4]Peter Gutberlet, Wolfgang Rosenstiel:
Interface specification and synthesis for VHDL processes. EURO-DAC 1993: 152-157 - 1992
- [c3]Peter Gutberlet, Jens Müller, Heinrich Krämer, Wolfgang Rosenstiel:
Automatic module allocation in high level synthesis. EURO-DAC 1992: 328-333 - 1991
- [c2]Peter Gutberlet, Heinrich Krämer, Wolfgang Rosenstiel:
CASCH: a scheduling algorithm for "high level"-synthesis. EURO-DAC 1991: 311-315 - 1990
- [c1]Peter Gutberlet, Heinrich Krämer, Wolfgang Rosenstiel:
CASCH - ein Scheduling-Algorithmus für "High-Level"-Synthese. Rechnergestützter Entwurf und Architektur mikroelektronischer Systeme 1990: 143-156
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