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ORCIDJan Craninckx
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- affiliation: imec, Leuven, Belgium
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2020 – today
- 2020
[j56]Cheng-Hsueh Tsai
, Zhiwei Zong, Federico Pepe, Giovanni Mangraviti, Jan Craninckx, Piet Wambacq:
Analysis of a 28-nm CMOS Fast-Lock Bang-Bang Digital PLL With 220-fs RMS Jitter for Millimeter-Wave Communication. IEEE J. Solid State Circuits 55(7): 1854-1863 (2020)- [j55]Pratap Tumkur Renukaswamy, Nereo Markulic, Piet Wambacq, Jan Craninckx:
A 12-mW 10-GHz FMCW PLL Based on an Integrating DAC With 28-kHz RMS-Frequency-Error for 23-MHz/μs Slope and 1.2-GHz Chirp-Bandwidth. IEEE J. Solid State Circuits 55(12): 3294-3307 (2020) - [c77]Zihao Zheng, Lai Wei, Jorge Lagos, Ewout Martens, Yan Zhu, Chi-Hang Chan, Jan Craninckx, Rui Paulo Martins:
16.3 A Single-Channel 5.5mW 3.3GS/s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation. ISSCC 2020: 254-256 - [c76]Pratap Tumkur Renukaswamy, Nereo Markulic, Sehoon Park, Anirudh Kankuppe, Qixian Shi, Piet Wambacq, Jan Craninckx:
17.7 A 12mW 10GHz FMCW PLL Based on an Integrating DAC with 90kHz rms Frequency Error for 23MHz/µs Slope and 1.2GHz Chirp Bandwidth. ISSCC 2020: 278-280 - [c75]Benjamin P. Hershberg, Nereo Markulic, Jorge Lagos, Ewout Martens, Davide Dermit, Jan Craninckx:
A 1MS/s to 1GS/s Ringamp-Based Pipelined ADC with Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16nm. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [j54]Jorge Lagos, Benjamin P. Hershberg, Ewout Martens, Piet Wambacq, Jan Craninckx:
A Single-Channel, 600-MS/s, 12-b, Ringamp-Based Pipelined ADC in 28-nm CMOS. IEEE J. Solid State Circuits 54(2): 403-416 (2019) - [j53]Jorge Lagos, Benjamin P. Hershberg, Ewout Martens, Piet Wambacq, Jan Craninckx:
A 1-GS/s, 12-b, Single-Channel Pipelined ADC With Dead-Zone-Degenerated Ring Amplifiers. IEEE J. Solid State Circuits 54(3): 646-658 (2019) - [j52]Nereo Markulic, Pratap Tumkur Renukaswamy, Ewout Martens, Barend van Liempd, Piet Wambacq, Jan Craninckx:
A 5.5-GHz Background-Calibrated Subsampling Polar Transmitter With -41.3-dB EVM at 1024 QAM in 28-nm CMOS. IEEE J. Solid State Circuits 54(4): 1059-1073 (2019) - [j51]Jan Craninckx:
New Associate Editors. IEEE J. Solid State Circuits 54(6): 1515-1516 (2019) - [j50]Jan Craninckx:
Message From the Outgoing Editor-in-Chief. IEEE J. Solid State Circuits 54(8): 2107 (2019) - [j49]Qixian Shi, Keigo Bunsen, Nereo Markulic, Jan Craninckx:
A Self-Calibrated 16-GHz Subsampling-PLL-Based Fast-Chirp FMCW Modulator With 1.5-GHz Bandwidth. IEEE J. Solid State Circuits 54(12): 3503-3512 (2019) - [j48]Shiwei Wang, Carolina Mora Lopez, Seyed Kasra Garakoui, Ho Sung Chun, Didac Gomez Salinas, Wim Sijbers, Jan Putzeys, Ewout Martens, Jan Craninckx, Nick Van Helleputte:
A Compact Quad-Shank CMOS Neural Probe With 5, 120 Addressable Recording Sites and 384 Fully Differential Parallel Channels. IEEE Trans. Biomed. Circuits Syst. 13(6): 1625-1634 (2019) - [c74]Aritra Banerjee, Kristof Vaesen, Akshay Visweswaran, Khaled Khalaf, Qixian Shi, Steven Brebels, Davide Guermandi, Cheng-Hsueh Tsai, Johan Nguyen, Alaa Medra, Yao Liu, Giovanni Mangraviti, Orges Furxhi, Bert Gyselinckx, André Bourdoux, Jan Craninckx, Piet Wambacq:
Millimeter-Wave Transceivers for Wireless Communication, Radar, and Sensing : (Invited Paper). CICC 2019: 1-11 - [c73]Cheng-Hsueh Tsai, Federico Pepe, Giovanni Mangraviti, Zhiwei Zong, Jan Craninckx, Piet Wambacq:
A 22.5-27.7-GHz Fast-Lock Bang-Bang Digital PLL in 28-nm CMOS for Millimeter-Wave Communication With 220-fs RMS Jitter. ESSCIRC 2019: 111-114 - [c72]Benjamin P. Hershberg, Davide Dermit, Barend van Liempd, Ewout Martens, Nereo Markulic, Jorge Lagos, Jan Craninckx:
A 3.2GS/s 10 ENOB 61mW Ringamp ADC in 16nm with Background Monitoring of Distortion. ISSCC 2019: 58-60 - [c71]Benjamin P. Hershberg, Barend van Liempd, Nereo Markulic, Jorge Lagos, Ewout Martens, Davide Dermit, Jan Craninckx:
A 6-to-600MS/s Fully Dynamic Ringamp Pipelined ADC with Asynchronous Event-Driven Clocking in 16nm. ISSCC 2019: 68-70 - [c70]Qixian Shi, Keigo Bunsen, Nereo Markulic, Jan Craninckx:
A Self-Calibrated 16GHz Subsampling-PLL-Based 30s Fast Chirp FMCW Modulator with 1.5GHz Bandwidth and 100kHz rms Error. ISSCC 2019: 408-410 - 2018
- [j47]Jan Craninckx:
New Associate Editors. IEEE J. Solid State Circuits 53(4): 963-964 (2018) - [j46]Ewout Martens, Benjamin P. Hershberg, Jan Craninckx:
A 69-dB SNDR 300-MS/s Two-Time Interleaved Pipelined SAR ADC in 16-nm CMOS FinFET With Capacitive Reference Stabilization. IEEE J. Solid State Circuits 53(4): 1161-1171 (2018) - [j45]Jan Craninckx:
New Associate Editor. IEEE J. Solid State Circuits 53(5): 1243 (2018) - [j44]Gengzhen Qi, Barend van Liempd, Pui-In Mak, Rui Paulo Martins, Jan Craninckx:
A SAW-Less Tunable RF Front End for FDD and IBFD Combining an Electrical-Balance Duplexer and a Switched-LC N-Path LNA. IEEE J. Solid State Circuits 53(5): 1431-1442 (2018) - [j43]Jan Craninckx:
New Associate Editor. IEEE J. Solid State Circuits 53(7): 1875 (2018) - [j42]Lin-Kun Wu, David San Segundo Bello, Philippe Coppejans, Jan Craninckx, Andreas Süss, Maarten Rosmeulen, Piet Wambacq, Jonathan Borremans:
Analysis and Design of a CMOS Ultra-High-Speed Burst Mode Imager with In-Situ Storage Topology Featuring In-Pixel CDS Amplification. Sensors 18(11): 3683 (2018) - [c69]Jorge Lagos, Benjamin P. Hershberg, Ewout Martens, Piet Wambacq, Jan Craninckx:
A 1Gsps, 12-bit, single-channel pipelined ADC with dead-zone-degenerated ring amplifiers. CICC 2018: 1-4 - [c68]Nereo Markulic, Pratap Renukaswarny, Ewout Martens, Barend van Liempd, Piet Wambacq, Jan Craninckx:
A 5.5 GHz Background-Calibrated Subsampling Polar Transmitter with -41.3 DB EVM at 1024 OAM in 28NM CMOS. VLSI Circuits 2018: 215-216 - 2017
- [j41]Jan Craninckx:
New Associate Editor. IEEE J. Solid State Circuits 52(4): 887 (2017) - [j40]Jan Craninckx:
New Associate Editor. IEEE J. Solid State Circuits 52(7): 1699 (2017) - [j39]Jan Craninckx:
New Associate Editor. IEEE J. Solid State Circuits 52(9): 2223 (2017) - [j38]John R. Long, Jan Craninckx, Behzad Razavi:
Introducing Our Sister Publication: IEEE Solid-State Circuits Letters. IEEE J. Solid State Circuits 52(10): 2519-2520 (2017) - [j37]Davide Guermandi, Qixian Shi, Andy Dewilde, Veerle Derudder, Ubaid Ahmad, Annachiara Spagnolo, Ilja Ocket, André Bourdoux, Piet Wambacq, Jan Craninckx, Wim Van Thillo:
A 79-GHz 2 × 2 MIMO PMCW Radar SoC in 28-nm CMOS. IEEE J. Solid State Circuits 52(10): 2613-2626 (2017) - [c67]Mark Ingels, Davide Dermit, Yao Liu, Hans Cappelle, Jan Craninckx:
A 2×14bit digital transmitter with memoryless current unit cells and integrated AM/PM calibration. ESSCIRC 2017: 324-327 - [c66]Alyosha C. Molnar, Jan Craninckx, Aarno Pärssinen:
Session 18 overview: Full duplex wireless front-ends. ISSCC 2017: 312-313 - [c65]Jiayoon Ru, Kohei Onizuka, Pavan Hanumolu, Roberto Nonis, Howard Luong, Jan Craninckx:
F2: High-performance frequency generation for wireless and wireline systems. ISSCC 2017: 503-505 - 2016
- [j36]Badr Malki, Bob Verbruggen, Ewout Martens, Piet Wambacq, Jan Craninckx:
A 150 kHz-80 MHz BW Discrete-Time Analog Baseband for Software-Defined-Radio Receivers using a 5th-Order IIR LPF, Active FIR and a 10 bit 300 MS/s ADC in 28 nm CMOS. IEEE J. Solid State Circuits 51(7): 1593-1606 (2016) - [j35]Jan Craninckx:
Message From the Incoming Editor-in-Chief. IEEE J. Solid State Circuits 51(8): 1732 (2016) - [j34]Jan Craninckx:
50th Anniversary of the Journal. IEEE J. Solid State Circuits 51(11): 2519 (2016) - [j33]Nereo Markulic, Kuba Raczkowski, Ewout Martens, Pedro Emiliano Paro Filho, Benjamin P. Hershberg, Piet Wambacq, Jan Craninckx:
A DTC-Based Subsampling PLL Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation. IEEE J. Solid State Circuits 51(12): 3078-3092 (2016) - [c64]Nereo Markulic, Kuba Raczkowski, Ewout Martens, Pedro Emiliano Paro Filho, Benjamin P. Hershberg, Piet Wambacq, Jan Craninckx:
9.7 A self-calibrated 10Mb/s phase modulator with -37.4dB EVM based on a 10.1-to-12.4GHz, -246.6dB-FOM, fractional-N subsampling PLL. ISSCC 2016: 176-177 - [c63]Pedro Emiliano Paro Filho, Mark Ingels, Piet Wambacq, Jan Craninckx:
13.7 A 0.22mm2 CMOS resistive charge-based direct-launch digital transmitter with -159dBc/Hz out-of-band noise. ISSCC 2016: 250-252 - [c62]Benjamin P. Hershberg, Barend van Liempd, Xiaoqiang Zhang, Piet Wambacq, Jan Craninckx:
20.8 A dual-frequency 0.7-to-1GHz balance network for electrical balance duplexers. ISSCC 2016: 356-357 - [c61]Stefano Pellerano, Ahmad Mirzaei, Chih-Ming Hung, Jan Craninckx, Kenichi Okada, Vojkan Vidojkovic:
F3: Radio architectures and circuits towards 5G. ISSCC 2016: 498-501 - [c60]Harish Krishnaswamy, Jan Craninckx, Tae Wook Kim:
EE2: Do we need to downscale our radios below 20nm? ISSCC 2016: 519 - [c59]Nereo Markulic, Kuba Raczkowski, Piet Wambacq, Jan Craninckx:
A Fractional-n subsampling PLL based on a digital-to-time converter. MIPRO 2016: 66-71 - 2015
- [j32]Badr Malki, Takaya Yamamoto, Bob Verbruggen, Piet Wambacq, Jan Craninckx:
Correction to "A 70 dB DR 10 b 0-to-80 MS/s Current-Integrating SAR ADC With Adaptive Dynamic Range". IEEE J. Solid State Circuits 50(2): 619 (2015) - [j31]Kuba Raczkowski, Nereo Markulic, Benjamin P. Hershberg, Jan Craninckx:
A 9.2-12.7 GHz Wideband Fractional-N Subsampling PLL in 28 nm CMOS With 280 fs RMS Jitter. IEEE J. Solid State Circuits 50(5): 1203-1213 (2015) - [j30]Bob Verbruggen, Jorgo Tsouhlarakis, Takaya Yamamoto, Masao Iriguchi, Ewout Martens, Jan Craninckx:
A 60 dB SNDR 35 MS/s SAR ADC With Comparator-Noise-Based Stochastic Residue Estimation. IEEE J. Solid State Circuits 50(9): 2002-2011 (2015) - [j29]Pedro Emiliano Paro Filho, Mark Ingels, Piet Wambacq, Jan Craninckx:
An Incremental-Charge-Based Digital Transmitter With Built-in Filtering. IEEE J. Solid State Circuits 50(12): 3065-3076 (2015) - [j28]Chunshu Li, Min Li, Khaled Khalaf, André Bourdoux, Marian Verhelst, Mark Ingels, Piet Wambacq, Jan Craninckx, Liesbet Van der Perre, Sofie Pollin:
Opportunities and Challenges of Digital Signal Processing in Deeply Technology-Scaled Transceivers. J. Signal Process. Syst. 78(1): 5-19 (2015) - [c58]Qixian Shi, Davide Guermandi, Jan Craninckx, Piet Wambacq:
Flicker noise upconversion mechanisms in K-band CMOS VCOs. A-SSCC 2015: 1-4 - [c57]Badr Malki, Bob Verbruggen, Ewout Martens, Piet Wambacq, Jan Craninckx:
A 150 kHz-80 MHz BW DT analog baseband for SDR RX using a 5th-order IIR LPF, active FIR and 10b 300 MS/s ADC in 28nm CMOS. ESSCIRC 2015: 80-83 - [c56]Björn Debaillie, Barend van Liempd, Benjamin P. Hershberg, Jan Craninckx, Kari Rikkinen, D. J. van den Broek, Eric A. M. Klumperink, Bram Nauta:
In-band full-duplex transceiver technology for 5G mobile networks. ESSCIRC 2015: 84-87 - [c55]Barend van Liempd, Saneaki Ariumi, Ewout Martens, Shih-Hung Chen, Piet Wambacq, Jan Craninckx:
A 0.7-1.15GHz complementary common-gate LNA in 0.18μm SOI CMOS with +15dBm IIP3 and >1kV HBM ESD protection. ESSCIRC 2015: 164-167 - [c54]Barend van Liempd, Benjamin P. Hershberg, Björn Debaillie, Piet Wambacq, Jan Craninckx:
An electrical-balance duplexer for in-band full-duplex with <-85dBm in-band distortion at +10dBm TX-power. ESSCIRC 2015: 176-179 - [c53]Pedro Emiliano Paro Filho, Mark Ingels, Piet Wambacq, Jan Craninckx:
9.3 A transmitter with 10b 128MS/S incremental-charge-based DAC achieving -155dBc/Hz out-of-band noise. ISSCC 2015: 1-3 - [c52]Barend van Liempd, Benjamin P. Hershberg, Kuba Raczkowski, Saneaki Ariumi, Udo Karthaus, Karl-Frederik Bink, Jan Craninckx:
2.2 A +70dBm IIP3 single-ended electrical-balance duplexer in 0.18um SOI CMOS. ISSCC 2015: 1-3 - 2014
- [j27]Björn Debaillie, Dirk-Jan van den Broek, Cristina Lavin, Barend van Liempd, Eric A. M. Klumperink, Carmen Palacios, Jan Craninckx, Bram Nauta, Aarno Pärssinen:
Analog/RF Solutions Enabling Compact Full-Duplex Radios. IEEE J. Sel. Areas Commun. 32(9): 1662-1673 (2014) - [j26]Badr Malki, Takaya Yamamoto, Bob Verbruggen, Piet Wambacq, Jan Craninckx:
A 70 dB DR 10 b 0-to-80 MS/s Current-Integrating SAR ADC With Adaptive Dynamic Range. IEEE J. Solid State Circuits 49(5): 1173-1183 (2014) - [j25]Barend van Liempd, Jonathan Borremans, Ewout Martens, Sungwoo Cha, Hans Suys, Bob Verbruggen, Jan Craninckx:
A 0.9 V 0.4-6 GHz Harmonic Recombination SDR Receiver in 28 nm CMOS With HR3/HR5 and IIP2 Calibration. IEEE J. Solid State Circuits 49(8): 1815-1826 (2014) - [c51]Mina Mikhael, Barend van Liempd, Jan Craninckx, Rafik Guindi, Björn Debaillie:
A Full-Duplex Transceiver Prototype with In-System Automated Tuning of the RF Self-Interference Cancellation. 5GU 2014: 110-115 - [c50]Barend van Liempd, Björn Debaillie, Jan Craninckx, Cristina Lavin, Carmen Palacios, S. Malotaux, John R. Long, D. J. van den Broek, Eric A. M. Klumperink:
RF self-interference cancellation for full-duplex. CrownCom 2014: 526-531 - [c49]Nereo Markulic, Kuba Raczkowski, Piet Wambacq, Jan Craninckx:
A 10-bit, 550-fs step Digital-to-Time Converter in 28nm CMOS. ESSCIRC 2014: 79-82 - [c48]Benjamin P. Hershberg, Kuba Raczkowski, Kristof Vaesen, Jan Craninckx:
A 9.1-12.7 GHz VCO in 28nm CMOS with a bottom-pinning bias technique for digital varactor stress reduction. ESSCIRC 2014: 83-86 - [c47]Badr Malki, Bob Verbruggen, Piet Wambacq, Kazuaki Deguchi, Masao Iriguchi, Jan Craninckx:
A complementary dynamic residue amplifier for a 67 dB SNDR 1.36 mW 170 MS/s pipelined SAR ADC. ESSCIRC 2014: 215-218 - [c46]Mark Ingels, Xiaoqiang Zhang, Kuba Raczkowski, Sungwoo Cha, Pieter Palmers, Jan Craninckx:
A linear 28nm CMOS digital transmitter with 2×12bit up to LO baseband sampling and -58dBc C-IM3. ESSCIRC 2014: 379-382 - [c45]Barend van Liempd, Jan Craninckx, R. Singh, Patrick Reynaert, S. Malotaux, John R. Long:
A dual-notch +27dBm Tx-power electrical-balance duplexer. ESSCIRC 2014: 463-466 - [c44]Vito Giannini, Davide Guermandi, Qixian Shi, Kristof Vaesen, Bertrand Parvais, Wim Van Thillo, André Bourdoux, Charlotte Soens, Jan Craninckx, Piet Wambacq:
14.2 A 79GHz phase-modulated 4GHz-BW CW radar TX in 28nm CMOS. ISSCC 2014: 250-251 - [c43]Bob Verbruggen, Kazuaki Deguchi, Badr Malki, Jan Craninckx:
A 70 dB SNDR 200 MS/s 2.3 mW dynamic pipelined SAR ADC in 28nm digital CMOS. VLSIC 2014: 1-2 - 2013
- [j24]Vincenzo Chironi, Björn Debaillie, Stefano D'Amico, Andrea Baschirotto, Jan Craninckx, Mark Ingels:
A Digitally Modulated Class-E Polar Amplifier in 90 nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(4): 918-925 (2013) - [c42]Barend van Liempd, Jonathan Borremans, Sungwoo Cha, Ewout Martens, Hans Suys, Jan Craninckx:
IIP2 and HR calibration for an 8-phase harmonic recombination receiver in 28nm. CICC 2013: 1-4 - [c41]Mark Ingels, Yoshikazu Furuta, Xiaoqiang Zhang, Sungwoo Cha, Jan Craninckx:
A multiband 40nm CMOS LTE SAW-less modulator with -60dBc C-IM3. ISSCC 2013: 338-339 - [c40]Min Li, Khaled Khalaf, Chunshu Li, Vojkan Vidojkovic, Mark Ingels, André Bourdoux, Piet Wambacq, Jan Craninckx, Liesbet Van der Perre:
Signal processing challenges for emerging digital intensive and digitally assisted transceivers with deeply scaled technology (Invited). SiPS 2013: 324-329 - 2012
- [j23]Jan Craninckx:
CMOS software-defined radio transceivers: Analog design in digital technology. IEEE Commun. Mag. 50(4): 136-144 (2012) - [j22]Ewout Martens, André Bourdoux, Aïssa Couvreur, Robert Fasthuber, Peter Van Wesemael, Geert Van der Plas, Jan Craninckx, Julien Ryckaert:
RF-to-Baseband Digitization in 40 nm CMOS With RF Bandpass ΔΣ Modulator and Polyphase Decimation Filter. IEEE J. Solid State Circuits 47(4): 990-1002 (2012) - [j21]Bob Verbruggen, Masao Iriguchi, Jan Craninckx:
A 1.7 mW 11b 250 MS/s 2-Times Interleaved Fully Dynamic Pipelined SAR ADC in 40 nm Digital CMOS. IEEE J. Solid State Circuits 47(12): 2880-2887 (2012) - [j20]Pierluigi Nuzzo, Claudio Nani, Costantino Armiento, Alberto L. Sangiovanni-Vincentelli, Jan Craninckx, Geert Van der Plas:
A 6-Bit 50-MS/s Threshold Configuring SAR ADC in 90-nm Digital CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(1): 80-92 (2012) - [c39]Peng Gao, Xinpeng Xing, Jan Craninckx, Georges G. E. Gielen:
Design of an intrinsically-linear double-VCO-based ADC with 2nd-order noise shaping. DATE 2012: 1215-1220 - [c38]Wagdy M. Gaber, Piet Wambacq, Jan Craninckx, Mark Ingels:
A CMOS IQ Digital Doherty Transmitter using modulated tuning capacitors. ESSCIRC 2012: 341-344 - [c37]Bob Verbruggen, Masao Iriguchi, Jan Craninckx:
A 1.7mW 11b 250MS/s 2× interleaved fully dynamic pipelined SAR ADC in 40nm digital CMOS. ISSCC 2012: 466-468 - [c36]Badr Malki, Takaya Yamamoto, Bob Verbruggen, Piet Wambacq, Jan Craninckx:
A 70dB DR 10b 0-to-80MS/s current-integrating SAR ADC with adaptive dynamic range. ISSCC 2012: 470-472 - 2011
- [j19]Jonathan Borremans, Gunjan Mandal, Vito Giannini, Björn Debaillie, Mark Ingels, Tomohiro Sano, Bob Verbruggen, Jan Craninckx:
A 40 nm CMOS 0.4-6 GHz Receiver Resilient to Out-of-Band Blockers. IEEE J. Solid State Circuits 46(7): 1659-1671 (2011) - [c35]Mark Ingels, Vincenzo Chironi, Björn Debaillie, Andrea Baschirotto, Jan Craninckx:
An impedance modulated class-E polar amplifier in 90 nm CMOS. A-SSCC 2011: 285-288 - [c34]Jan Craninckx, Jonathan Borremans, Mark Ingels:
SAW-less software-defined radio transceivers in 40nm CMOS. CICC 2011: 1-8 - [c33]Wagdy M. Gaber, Piet Wambacq, Jan Craninckx, Mark Ingels:
A CMOS IQ direct digital RF modulator with embedded RF FIR-based quantization noise filter. ESSCIRC 2011: 139-142 - [c32]Kameswaran Vengattaramane, Jonathan Borremans, Michiel Steyaert, Jan Craninckx:
A standard cell based all-digital Time-to-Digital Converter with reconfigurable resolution and on-line background calibration. ESSCIRC 2011: 275-278 - [c31]Jonathan Borremans, Gunjan Mandal, Vito Giannini, Tomohiro Sano, Mark Ingels, Bob Verbruggen, Jan Craninckx:
A 40nm CMOS highly linear 0.4-to-6GHz receiver resilient to 0dBm out-of-band blockers. ISSCC 2011: 62-64 - [c30]Vito Giannini, Mark Ingels, Tomohiro Sano, Björn Debaillie, Jonathan Borremans, Jan Craninckx:
A multiband LTE SAW-less modulator with -160dBc/Hz RX-band noise in 40nm LP CMOS. ISSCC 2011: 374-376 - [p1]Jan Craninckx, Geert Van der Plas:
Low-Power ADCs for Bio-Medical Applications. Bio-Medical CMOS ICs 2011: 157-190 - 2010
- [j18]Pieter Crombez, Geert Van der Plas, Michiel Steyaert, Jan Craninckx:
A Single-Bit 500 kHz-10 MHz Multimode Power-Performance Scalable 83-to-67 dB DR CTΔΣ for SDR in 90 nm Digital CMOS. IEEE J. Solid State Circuits 45(6): 1159-1171 (2010) - [j17]Bob Verbruggen, Jan Craninckx, Maarten Kuijk, Piet Wambacq, Geert Van der Plas:
A 2.6 mW 6 bit 2.2 GS/s Fully Dynamic Pipeline ADC in 40 nm Digital CMOS. IEEE J. Solid State Circuits 45(10): 2080-2090 (2010) - [j16]Jonathan Borremans, Kameswaran Vengattaramane, Vito Giannini, Björn Debaillie, Wim Van Thillo, Jan Craninckx:
A 86 MHz-12 GHz Digital-Intensive PLL for Software-Defined Radios, Using a 6 fJ/Step TDC in 40 nm Digital CMOS. IEEE J. Solid State Circuits 45(10): 2116-2129 (2010) - [j15]Arnd Geis, Julien Ryckaert, Lynn Bos, Gerd Vandersteen, Yves Rolain, Jan Craninckx:
A 0.5 mm 2 Power-Scalable 0.5-3.8-GHz CMOS DT-SDR Receiver With Second-Order RF Band-Pass Sampler. IEEE J. Solid State Circuits 45(11): 2375-2387 (2010) - [j14]Mark Ingels, Vito Giannini, Jonathan Borremans, Gunjan Mandal, Björn Debaillie, Peter Van Wesemael, Tomohiro Sano, Takaya Yamamoto, Dries Hauspie, Joris Van Driessche, Jan Craninckx:
A 5 mm2 40 nm LP CMOS Transceiver for a Software-Defined Radio Platform. IEEE J. Solid State Circuits 45(12): 2794-2806 (2010) - [c29]Arnd Geis, Pierluigi Nuzzo, Julien Ryckaert, Yves Rolain, Gerd Vandersteen, Jan Craninckx:
An 11.6-19.3mW 0.375-13.6GHz CMOS frequency synthesizer with rail-to-rail operation. DATE 2010: 697-701 - [c28]Vincenzo Chironi, Björn Debaillie, Andrea Baschirotto, Jan Craninckx, Mark Ingels:
A compact digital amplitude modulator in 90nm CMOS. DATE 2010: 702-705 - [c27]Jonathan Borremans, Gunjan Mandal, Björn Debaillie, Vito Giannini, Jan Craninckx:
A sub-3dB NF voltage-sampling front-end with +18dBm IIP3 and +2dBm blocker compression point. ESSCIRC 2010: 402-405 - [c26]Vincenzo Chironi, Björn Debaillie, Andrea Baschirotto, Jan Craninckx, Mark Ingels:
An area efficient digital amplitude modulator in 90nm CMOS. ISCAS 2010: 2219-2222 - [c25]Bob Verbruggen, Jan Craninckx, Maarten Kuijk, Piet Wambacq, Geert Van der Plas:
A 2.6mW 6b 2.2GS/s 4-times interleaved fully dynamic pipelined ADC in 40nm digital CMOS. ISSCC 2010: 296-297 - [c24]Mark Ingels, Vito Giannini, Jonathan Borremans, Gunjan Mandal, Björn Debaillie, Peter Van Wesemael, Tomohiro Sano, Takaya Yamamoto, Dries Hauspie, Joris Van Driessche, Jan Craninckx:
A 5mm2 40nm LP CMOS 0.1-to-3GHz multistandard transceiver. ISSCC 2010: 458-459 - [c23]Jonathan Borremans, Kameswaran Vengattaramane, Kameswaran Giannini, Jan Craninckx:
A 86MHz-to-12GHz digital-intensive phase-modulated fractional-N PLL using a 15pJ/Shot 5ps TDC in 40nm digital CMOS. ISSCC 2010: 480-481 - [c22]Stefan Heinen, Domine Leenaerts, Trudy Stetzler, Yiannos Manoli, Jan Craninckx, Ali Niknejad, Didier Belot, Raf Roovers, K. P. Pun, Jed Hurwitz:
Reconfigurable RF and data converters. ISSCC 2010: 512-513
2000 – 2009
- 2009
- [b1]Liesbet Van der Perre, Jan Craninckx, Antoine Dejonghe:
Green Software Defined Radios - Enabling seamless connectivity while saving on hardware and energy. Series on Integrated Circuits and Systems, Springer 2009, ISBN 978-1-4020-8210-8, pp. 1-157 - [j13]Bob Verbruggen, Jan Craninckx, Maarten Kuijk, Piet Wambacq, Geert Van der Plas:
A 2.2 mW 1.75 GS/s 5 Bit Folding Flash ADC in 90 nm Digital CMOS. IEEE J. Solid State Circuits 44(3): 874-882 (2009) - [j12]Jonathan Borremans, Julien Ryckaert, Claude Desset, Maarten Kuijk, Piet Wambacq, Jan Craninckx:
A Low-Complexity, Low-Phase-Noise, Low-Voltage Phase-Aligned Ring Oscillator in 90 nm Digital CMOS. IEEE J. Solid State Circuits 44(7): 1942-1949 (2009) - [j11]Julien Ryckaert, Jonathan Borremans, Bob Verbruggen, Lynn Bos, Costantino Armiento, Jan Craninckx, Geert Van der Plas:
A 2.4 GHz Low-Power Sixth-Order RF Bandpass ΔΣ Converter in CMOS. IEEE J. Solid State Circuits 44(11): 2873-2880 (2009) - [j10]Vito Giannini, Pierluigi Nuzzo, Charlotte Soens, Kameswaran Vengattaramane, Julien Ryckaert, Michaël Goffioul, Björn Debaillie, Jonathan Borremans, Joris Van Driessche, Jan Craninckx, Mark Ingels:
A 2-mm2 0.1-5 GHz Software-Defined Radio Receiver in 45-nm Digital CMOS. IEEE J. Solid State Circuits 44(12): 3486-3498 (2009) - [j9]Björn Debaillie, Peter Van Wesemael, Gerd Vandersteen, Jan Craninckx:
Calibration of Direct-Conversion Transceivers. IEEE J. Sel. Top. Signal Process. 3(3): 488-498 (2009) - [c21]Yi Ke, Jan Craninckx, Georges G. E. Gielen:
A design methodology for fully reconfigurable Delta-Sigma data converters. DATE 2009: 1379-1384 - [c20]Pieter Crombez, Geert Van der Plas, Michiel Steyaert, Jan Craninckx:
A single bit 6.8mW 10MHz power-optimized continuous-time ΔΣ with 67dB DR in 90nm CMOS. ESSCIRC 2009: 336-339 - [c19]Kameswaran Vengattaramane, Jan Craninckx, Michiel Steyaert:
Analysis of Fractional Spur Reduction using SigmaDelta-noise Cancellation in Digital-PLL. ISCAS 2009: 2397-2400 - [c18]Vito Giannini, Pierluigi Nuzzo, Charlotte Soens, Kameswaran Vengattaramane, Michiel Steyaert, Julien Ryckaert, Michaël Goffioul, Björn Debaillie, Joris Van Driessche, Jan Craninckx, Mark Ingels:
A 2mm2 0.1-to-5GHz SDR receiver in 45nm digital CMOS. ISSCC 2009: 408-409 - [c17]Jan Craninckx:
Clock synthesis design. ISSCC 2009: 510 - 2008
- [j8]Willem Laflere, Michiel S. J. Steyaert, Jan Craninckx:
A Polar Modulator Using Self-Oscillating Amplifiers and an Injection-Locked Upconversion Mixer. IEEE J. Solid State Circuits 43(2): 460-467 (2008) - [j7]Jonathan Borremans, Andrea Bevilacqua, Stephane Bronckers, Morin Dehan, Maarten Kuijk, Piet Wambacq, Jan Craninckx:
A Compact Wideband Front-End Using a Single-Inductor Dual-Band VCO in 90 nm Digital CMOS. IEEE J. Solid State Circuits 43(12): 2693-2705 (2008) - [j6]Pieter Crombez, Jan Craninckx, Piet Wambacq, Michiel Steyaert:
A 100-kHz to 20-MHz Reconfigurable Power-Linearity Optimized Gm-C Biquad in 0.13-mu m CMOS. IEEE Trans. Circuits Syst. II Express Briefs 55-II(3): 224-228 (2008) - [j5]Yi Ke, Jan Craninckx, Georges G. E. Gielen:
A Design Approach for Power-Optimized Fully Reconfigurable Delta Sigma A/D Converter for 4G Radios. IEEE Trans. Circuits Syst. II Express Briefs 55-II(3): 229-233 (2008) - [c16]Jonathan Borremans, Julien Ryckaert, Piet Wambacq, Maarten Kuijk, Jan Craninckx:
A low-complexity, low phase noise, low-voltage phase-aligned ring oscillator in 90 nm digital CMOS. ESSCIRC 2008: 410-413 - [c15]Björn Debaillie, Peter Van Wesemael, Jan Craninckx:
Calibration of SDR Circuit Imperfections. GLOBECOM 2008: 4700-4704 - [c14]Björn Debaillie, Peter Van Wesemael, Jan Craninckx:
Calibration Method Enabling Low-Cost SDR. ICC 2008: 4899-4903 - [c13]Vito Giannini, Pierluigi Nuzzo, Vincenzo Chironi, Andrea Baschirotto, Geert Van der Plas, Jan Craninckx:
An 820μW 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC in 90nm Digital CMOS. ISSCC 2008: 238-239 - [c12]