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2010 – 2019
- 2012
[j2]Ming-Hsien Tu, Jihi-Yu Lin, Ming-Chien Tsai, Chien-Yu Lu, Yuh-Jiun Lin, Meng-Hsueh Wang, Huan-Shun Huang, Kuen-Di Lee, Wei-Chiang Shih, Shyh-Jye Jou, Ching-Te Chuang:
A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing. IEEE J. Solid State Circuits 47(6): 1469-1482 (2012)- [c8]Shao-Cheng Wang, Geng-Cing Lin, Yi-Wei Lin, Ming-Chien Tsai, Yi-Wei Chiu, Shyh-Jye Jou, Ching-Te Chuang, Nan-Chun Lien, Wei-Chiang Shih, Kuen-Di Lee, Jyun-Kai Chu:
Design and implementation of dynamic Word-Line pulse write margin monitor for SRAM. APCCAS 2012: 116-119 - [c7]Geng-Cing Lin, Shao-Cheng Wang, Yi-Wei Lin, Ming-Chien Tsai, Ching-Te Chuang, Shyh-Jye Jou, Nan-Chun Lien, Wei-Chiang Shih, Kuen-Di Lee, Jyun-Kai Chu:
An all-digital bit transistor characterization scheme for CMOS 6T SRAM array. ISCAS 2012: 2485-2488 - [c6]Yi-Wei Lin, Ming-Chien Tsai, Hao-I Yang, Geng-Cing Lin, Shao-Cheng Wang, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang, Nan-Chun Lien, Kuen-Di Lee, Wei-Chiang Shih:
An all-digital Read Stability and Write Margin characterization scheme for CMOS 6T SRAM array. VLSI-DAT 2012: 1-4 - [c5]Ming-Chien Tsai, Yi-Wei Lin, Hao-I Yang, Ming-Hsien Tu, Wei-Chiang Shih, Nan-Chun Lien, Kuen-Di Lee, Shyh-Jye Jou, Ching-Te Chuang, Wei Hwang:
Embedded SRAM ring oscillator for in-situ measurement of NBTI and PBTI degradation in CMOS 6T SRAM array. VLSI-DAT 2012: 1-4 - 2010
- [j1]Ming-Hsien Tu, Jihi-Yu Lin, Ming-Chien Tsai, Shyh-Jye Jou, Ching-Te Chuang:
Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-Assist. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(12): 3039-3047 (2010)
2000 – 2009
- 2009
- [c4]Ming-Chien Tsai, Ching-Hwa Cheng:
A full-synthesizable high-precision built-in delay time measurement circuit. ASP-DAC 2009: 123-124 - [c3]Jihi-Yu Lin, Ming-Hsien Tu, Ming-Chien Tsai, Shyh-Jye Jou, Ching-Te Chuang:
Asymmetrical Write-assist for single-ended SRAM operation. SoCC 2009: 101-104 - 2008
- [c2]Ming-Chien Tsai, Ching-Hwa Cheng, Chiou-Mao Yang:
An All-Digital High-Precision Built-In Delay Time Measurement Circuit. VTS 2008: 249-254 - 2006
- [c1]Chiou-Kou Tung, Shao-Hui Shieh, Yu-Cherng Hung, Ming-Chien Tsai:
High-Performance Low-Power Full-Swing Full Adder Cores with Output Driving Capability. APCCAS 2006: 614-617
Coauthor Index
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