![](https://dblp.org/img/logo.ua.320x120.png)
![](https://dblp.org/img/dropdown.dark.16x16.png)
![](https://dblp.org/img/peace.dark.16x16.png)
Остановите войну!
for scientists:
![search dblp search dblp](https://dblp.org/img/search.dark.16x16.png)
![search dblp](https://dblp.org/img/search.dark.16x16.png)
default search action
Paulino Ruiz-de-Clavijo
Person information
Refine list
![note](https://dblp.org/img/note-mark.dark.12x12.png)
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
2020 – today
- 2020
- [j8]David Guerrero Martos
, Alejandro Millán Calderón, Jorge Juan-Chico, Julian Viejo
, Manuel Jesús Bellido Díaz
, Paulino Ruiz-de-Clavijo, Enrique Ostúa
:
Using the complement of the cosine to compute trigonometric functions. EURASIP J. Adv. Signal Process. 2020(1): 1-21 (2020) - [j7]David Guerrero Martos, German Cano-Quiveu
, Jorge Juan-Chico, Alejandro Millán, Manuel J. Bellido
, Julian Viejo
, Paulino Ruiz-de-Clavijo, Enrique Ostúa
:
Address-encoded byte order. Microprocess. Microsystems 78: 103268 (2020)
2010 – 2019
- 2018
- [c18]Alejandro Carrasco
, Jorge Ropero, Paulino Ruiz-de-Clavijo, Jaime Benjumea, Amalia Luque:
A Proposal for a New Way of Classifying Network Security Metrics: Study of the Information Collected through a Honeypot. QRS Companion 2018: 633-634 - 2017
- [j6]Paulino Ruiz-de-Clavijo, Enrique Ostúa
, Manuel Jesús Bellido Díaz
, Jorge Juan, Julian Viejo
, David Guerrero Martos:
Minimalistic SDHC-SPI hardware reader module for boot loader applications. Microelectron. J. 67: 32-37 (2017) - 2011
- [j5]David Guerrero Martos, Alejandro Millán
, Jorge Juan
, Manuel J. Bellido
, Paulino Ruiz-de-Clavijo
, Enrique Ostúa
, Julian Viejo
:
Studying the Viability of Static Complementary Metal-Oxide-Semiconductor Gates with a Large Number of Inputs When Using Separate Transistor Wells. J. Low Power Electron. 7(3): 444-452 (2011) - [j4]Julian Viejo
, Jorge Juan
, Manuel Jesús Bellido Díaz
, Alejandro Millán
, Paulino Ruiz-de-Clavijo
:
Fast-Convergence Microsecond-Accurate Clock Discipline Algorithm for Hardware Implementation. IEEE Trans. Instrum. Meas. 60(12): 3961-3963 (2011) - 2010
- [j3]Alejandro Millán
, Manuel J. Bellido
, Jorge Juan
, David Guerrero Martos, Paulino Ruiz-de-Clavijo
, Julian Viejo
:
Comprehensive Analysis on the Internal Power Dissipation of Static CMOS Cells in Ultra-Deep Sub-Micron Technologies. J. Low Power Electron. 6(1): 93-102 (2010)
2000 – 2009
- 2008
- [c17]Alejandro Millán
, Jorge Juan, Manuel J. Bellido
, David Guerrero Martos, Paulino Ruiz-de-Clavijo
, Julian Viejo
:
Power Dissipation Associated to Internal Effect Transitions in Static CMOS Gates. PATMOS 2008: 389-398 - 2007
- [j2]David Guerrero Martos, Alejandro Millán, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Paulino Ruiz-de-Clavijo, Enrique Ostúa
, Julian Viejo
:
Improving the Performance of Static CMOS Gates by Using Independent Bodies. J. Low Power Electron. 3(1): 70-77 (2007) - [c16]David Guerrero Martos, Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Enrique Ostúa
, Julian Viejo
:
Static Power Consumption in CMOS Gates Using Independent Bodies. PATMOS 2007: 404-412 - [c15]Julian Viejo
, Alejandro Millán
, Manuel J. Bellido
, Jorge Juan
, Paulino Ruiz-de-Clavijo
, David Guerrero Martos, Enrique Ostúa
, Alejandro Muñoz:
Design of a FFT/IFFT module as an IP core suitable for embedded systems. SIES 2007: 337-340 - 2006
- [j1]Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Alejandro Millán, David Guerrero Martos, Enrique Ostúa
, Julian Viejo
:
Accurate Logic-Level Current Estimation for Digital CMOS Circuits. J. Low Power Electron. 2(1): 87-94 (2006) - [c14]Julian Viejo
, Manuel J. Bellido
, Alejandro Millán
, Enrique Ostúa
, Jorge Juan
, Paulino Ruiz-de-Clavijo
, David Guerrero Martos:
Efficient Design and Implementation on FPGA of a MicroBlaze Peripheral for Processing Direct Electrical Networks Measurements. IES 2006: 1-7 - 2005
- [c13]Alejandro Millán Calderón, Manuel Jesús Bellido Díaz, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, David Guerrero Martos, Enrique Ostúa
, Julian Viejo
:
Application of Internode Model to Global Power Consumption Estimation in SCMOS Gates. PATMOS 2005: 337-347 - [c12]Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel Jesús Bellido Díaz, Alejandro Millán Calderón, David Guerrero Martos, Enrique Ostúa
, Julian Viejo
:
Logic-Level Fast Current Simulation for Digital CMOS Circuits. PATMOS 2005: 425-435 - 2004
- [c11]Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, David Guerrero Martos, Enrique Ostúa
:
Signal Sampling Based Transition Modeling for Digital Gates Characterization. PATMOS 2004: 829-837 - 2003
- [c10]Alejandro Millán, Manuel J. Bellido
, Jorge Juan-Chico
, David Guerrero Martos, Paulino Ruiz-de-Clavijo, Enrique Ostúa
:
Internode: Internal Node Logic Computational Model. Annual Simulation Symposium 2003: 241-248 - [c9]David Guerrero Martos, Gustavo Wilke, José Luís Almada Güntzel, Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Alejandro Millán:
Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits. PATMOS 2003: 501-510 - 2002
- [c8]Carmen Baena Oliva, Jorge Juan-Chico, Manuel J. Bellido
, Paulino Ruiz-de-Clavijo, Carlos Jesús Jiménez-Fernández, Manuel Valencia:
Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level. PATMOS 2002: 353-362 - [c7]Paulino Ruiz-de-Clavijo, Jorge Juan-Chico, Manuel J. Bellido
, Alejandro Millán, David Guerrero Martos:
Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level. PATMOS 2002: 400-408 - [c6]Alejandro Millán, Jorge Juan-Chico, Manuel J. Bellido
, Paulino Ruiz-de-Clavijo, David Guerrero Martos:
Characterization of Normal Propagation Delay for Delay Degradation Model (DDM). PATMOS 2002: 477-486 - 2001
- [c5]Paulino Ruiz-de-Clavijo
, Jorge Juan-Chico
, Manuel J. Bellido
, Antonio J. Acosta
, Manuel Valencia-Barrero:
HALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model. DATE 2001: 467-471 - [c4]Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Carmen Baena Oliva, Manuel Valencia
:
AUTODDM: automatic characterization tool for the delay degradation model. ICECS 2001: 1631-1634 - [c3]Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia-Barrero:
Gate-level simulation of CMOS circuits using the IDDM model. ISCAS (5) 2001: 483-486 - 2000
- [c2]Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Manuel J. Bellido, Antonio J. Acosta, Manuel Valencia:
Inertial and degradation delay model for CMOS logic gates. ISCAS 2000: 459-462 - [c1]Jorge Juan-Chico, Manuel J. Bellido
, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia-Barrero:
Degradation Delay Model Extension to CMOS Gates. PATMOS 2000: 149-158
Coauthor Index
![](https://dblp.org/img/cog.dark.24x24.png)
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from ,
, and
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and
to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from .
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-04-25 05:56 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint