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Philipp V. Panitz

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Conference and Workshop Papers

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2011
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Lei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler, Philipp V. Panitz:
A theoretical probabilistic simulation framework for dynamic power estimation. ICCAD 2011: 708-715
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Lei Wang, Markus Olbrich, Erich Barke, Thomas Büchner, Markus Bühler, Philipp V. Panitz:
A gate sizing method for glitch power reduction. SoCC 2011: 24-29
2008
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Philipp V. Panitz, Markus Olbrich, Erich Barke, Markus Bühler, Jürgen Koehl:
Considering possible opens in non-tree topology wire delay calculation. ACM Great Lakes Symposium on VLSI 2008: 17-22
2007
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Philipp V. Panitz, Markus Olbrich, Erich Barke, Jürgen Koehl:
Robust wiring networks for DfY considering timing constraints. ACM Great Lakes Symposium on VLSI 2007: 43-48

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