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ORCIDHussain Al-Asaad
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Books and Theses
- 1998
[b1]Hussain Al-Asaad:
Lifetime validation of digital systems via fault modeling and test generation. University of Michigan, USA, 1998
Journal Articles
- 2010
- [j6]Hussain Al-Asaad:
Efficient techniques for reducing error latency in on-line periodic built-in self-test. IEEE Instrum. Meas. Mag. 13(4): 28-32 (2010) - 2008
- [j5]Jorge Campos, Hussain Al-Asaad:
A Novel Mutation-Based Validation Paradigm for High-Level Hardware Descriptions. IEEE Trans. Very Large Scale Integr. Syst. 16(11): 1499-1512 (2008) - 2000
- [j4]Hussain Al-Asaad, John P. Hayes:
Logic Design Validation via Simulation and Automatic Test Pattern Generation. J. Electron. Test. 16(6): 575-589 (2000) - 1998
- [j3]Hussain Al-Asaad, Brian T. Murray, John P. Hayes:
Online BIST for Embedded Systems. IEEE Des. Test Comput. 15(4): 17-24 (1998) - [j2]Hussain Al-Asaad, John P. Hayes, Brian T. Murray:
Scalable Test Generators for High-Speed Datapath Circuits. J. Electron. Test. 12(1-2): 111-125 (1998) - [j1]David Van Campenhout, Hussain Al-Asaad, John P. Hayes, Trevor N. Mudge, Richard B. Brown:
High-level design verification of microprocessors via error modeling. ACM Trans. Design Autom. Electr. Syst. 3(4): 581-599 (1998)
Conference and Workshop Papers
- 2024
- [c25]Alireza Abolhasani Zeraatkar
, Parnian Shabani Kamran, Hussain Al-Asaad:
Advancements in Secure Computing: Exploring Automated Repair Debugging and Verification Techniques for Hardware Design. CCWC 2024: 357-364 - [c24]Alireza Abolhasani Zeraatkar, Parnian Shabani Kamran, Inderpreet Kaur, Nagabindu Ramu, Tyler Sheaves, Hussain Al-Asaad:
On the Performance of Malware Detection Classifiers Using Hardware Performance Counters. SmartNets 2024: 1-6 - 2022
- [c23]Raihana Yarzada, Divya Singh, Hussain Al-Asaad:
A Brief Survey of Fault Tolerant Techniques for Field Programmable Gate Arrays. CCWC 2022: 823-828 - 2010
- [c22]Calvin Chiem, Hussain Al-Asaad:
A Comparison of NMOS to PMOS Starved Buffer Implementations for the Delay Line in a PWM DC-DC Converters. CDES 2010: 10-16 - [c21]Hussain Al-Asaad:
Time-Redundant Logic-Level Protection Mechanisms from Soft Errors in Digital Systems. CDES 2010: 17-21 - 2009
- [c20]Hussain Al-Asaad:
Detection and Isolation of Faulty Processors in Multiprocessor Systems via TMR-Based Time Redundant Task Scheduling. CDES 2009: 42-47 - [c19]Calvin Chiem, Hussain Al-Asaad:
Low Power Methodologies and Challenges for PWM DC-DC Converters. CDES 2009: 70-75 - 2007
- [c18]Hussain Al-Asaad:
Efficient Global Fault Collapsing for Combinational Library Modules. CDES 2007: 37-43 - [c17]Ahmed Sayed, Hussain Al-Asaad:
A New Statistical Approach for Glitch Estimation in Combinational Circuits. ISCAS 2007: 1641-1644 - 2006
- [c16]Ahmed Sayed, Hussain Al-Asaad:
Survey and Evaluation of Low-Power Flip-Flops. CDES 2006: 77-83 - [c15]Jorge Campos, Hussain Al-Asaad:
Circuit Profiling Mechanisms for High-Level {ATPG}. MTV 2006: 9-14 - 2005
- [c14]Hector Arteaga, Hussain Al-Asaad:
On Increasing the Observability of Modern Microprocessors. CDES 2005: 91-96 - [c13]Hussain Al-Asaad, Ganesh Valliappan, Lourdes Ramirez:
A Novel Functional Testing and Verification Technique for Logic Circuits. CDES 2005: 129-135 - [c12]Jorge Campos, Hussain Al-Asaad:
MVP: a mutation-based validation paradigm. HLDVT 2005: 27-34 - [c11]Hussain Al-Asaad:
EGFC: An exact global fault collapsing tool for combinational circuits. Circuits, Signals, and Systems 2005: 56-61 - [c10]Jorge Campos, Hussain Al-Asaad:
Search-Space Optimizations for High-Level ATPG. MTV 2005: 84-89 - 2004
- [c9]Ahmed Sayed, Hussain Al-Asaad:
Survey and Evaluation of Low-Power Full-Adder Cells. ESA/VLSI 2004: 332-338 - [c8]Hector Arteaga, Hussain Al-Asaad:
Approaches for Monitoring Vectors on Microprocessor Buses. ESA/VLSI 2004: 393-398 - [c7]Jorge Campos, Hussain Al-Asaad:
Mutation-based validation of high-level microprocessor implementations. HLDVT 2004: 81-86 - 2003
- [c6]Hussain Al-Asaad, Alireza Sarvi:
Fault Tolerance for Multiprocessor Systems Via Time Redundant Task Scheduling. VLSI 2003: 51-57 - 2000
- [c5]Hussain Al-Asaad, John P. Hayes:
ESIM: A Multimodel Design Error and Fault Simulator for Logic Circuits. VTS 2000: 221-230 - 1995
- [c4]Hussain Al-Asaad, John P. Hayes:
Design verification via simulation and automatic test pattern generation. ICCAD 1995: 174-180 - 1994
- [c3]Hussain Al-Asaad, Mankuan Michael Vai, James Feldman:
Distributed Reconfiguration of Fault Tolerant VLSI Mulipipeline Arrays with Constant Interstage Path Lengths. ICCD 1994: 75-78 - 1993
- [c2]Hussain Al-Asaad, Elias S. Manolakos:
A Two-Phase Reconfiguration Strategy for Extracting Linear Arrays Out of Two-Dimensional Architectures. DFT 1993: 56-63 - [c1]Hussain Al-Asaad, Edward C. Czeck:
Concurrent error correction in iterative circuits by recomputing with partitioning and voting. VTS 1993: 174-177
Coauthor Index
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