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2020 – today
- 2023
[j4]Wei-Chen Wang
, Chien-Chung Ho, Yung-Chun Li, Liang-Chi Chen, Yu-Ming Chang:
Reaping Both Latency and Reliability Benefits With Elaborate Sanitization Design for 3D TLC NAND Flash. IEEE Trans. Computers 72(11): 3029-3041 (2023)- [j3]Shin-Ting Wu, Liang-Chi Chen, Po-Chun Huang, Yuan-Hao Chang, Chien-Chung Ho, Wei-Kuan Shih:
WARM-tree: Making Quadtrees Write-efficient and Space-economic on Persistent Memories. ACM Trans. Embed. Comput. Syst. 22(5s): 119:1-119:26 (2023) - [c13]Liang-Chi Chen, Chien-Chung Ho, Yuan-Hao Chang:
UpPipe: A Novel Pipeline Management on In-Memory Processors for RNA-seq Quantification. DAC 2023: 1-6 - [c12]Liang-Chi Chen, Shu-Qi Yu, Chien-Chung Ho, Wei-Chen Wang, Yung-Chun Li:
Efficient Sanitization Design for LSM-based Key-Value Store over 3D MLC NAND Flash. SAC 2023: 72-75 - 2022
- [j2]Jyun-Hong Lin, Liang-Chi Chen, Shu-Chi Yu, Yao-Ting Huang:
LongPhase: an ultra-fast chromosome-scale phasing algorithm for small and large variants. Bioinform. 38(7): 1816-1822 (2022) - [c11]Liang-Chi Chen, Shu-Qi Yu, Chien-Chung Ho, Yuan-Hao Chang, Da-Wei Chang, Wei-Chen Wang, Yu-Ming Chang:
RNA-seq Quantification on Processing in memory Architecture: Observation and Characterization. NVMSA 2022: 26-32 - 2020
- [c10]Chia-Hui Feng, Yu-Hsiu Hung, Chao-Kuang Yang, Liang-Chi Chen, Wen-Cheng Hsu, Shih-Hao Lin:
Applying Holo360 Video and Image Super-Resolution Generative Adversarial Networks to Virtual Reality Immersion. HCI (1) 2020: 569-584 - [c9]Chia-Hui Feng, Yu-Chun Lin, Yu-Hsiu Hung, Chao-Kuang Yang, Liang-Chi Chen, Shih-Wei Yeh, Shih-Hao Lin:
Research on Aesthetic Perception of Artificial Intelligence Style Transfer. HCI (38) 2020: 641-649
2010 – 2019
- 2011
- [c8]Liang-Chi Chen, Peter Dahlgren, Paul Dickinson, Scott Davidson:
Transition test bring-up and diagnosis on UltraSPARCTM processors. ITC 2011: 1-10
2000 – 2009
- 2009
- [c7]Liang-Chi Chen, Paul Dickinson, Peter Dahlgren, Scott Davidson, Olivier Caty, Kevin Wu:
Using transition test to understand timing behavior of logic circuits on UltraSPARCTM T2 family. ITC 2009: 1-10 - 2008
- [c6]Liang-Chi Chen, Paul Dickinson, Prasad Mantri, Murali M. R. Gala, Peter Dahlgren, Subhra Bhattacharya, Olivier Caty, Kevin Woodling, Thomas A. Ziaja, David Curwen, Wendy Yee, Ellen Su, Guixiang Gu, Tim Nguyen:
Transition Test on UltraSPARC- T2 Microprocessor. ITC 2008: 1-10 - 2002
- [j1]Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer:
TA-PSV - Timing Analysis for Partially Specified Vectors. J. Electron. Test. 18(1): 73-88 (2002) - 2001
- [c5]Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer:
A New Gate Delay Model for Simultaneous Switching and Its Applications. DAC 2001: 289-294 - [c4]Liang-Chi Chen, T. M. Mak, Sandeep K. Gupta, Melvin A. Breuer:
Crosstalk test generation on pseudo industrial circuits: a case study. ITC 2001: 548-557 - 2000
- [c3]Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer:
A new framework for static timing analysis, incremental timing refinement, and timing simulation. Asian Test Symposium 2000: 102-107
1990 – 1999
- 1997
- [c2]Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer:
High Quality Robust Tests for Path Delay Faults. VTS 1997: 88-93 - 1993
- [c1]Shambhu J. Upadhyaya, Liang-Chi Chen:
On-chip test generation for combinational circuits by LFSR modification. ICCAD 1993: 84-87
Coauthor Index
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