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ORCIDRani S. Ghaida
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2010 – 2019
- 2014
[c9]Rani S. Ghaida, Yasmine Badr, Mukul Gupta, Ning Jin, Puneet Gupta
:
Comprehensive die-level assessment of design rules and layouts. ASP-DAC 2014: 61-66- [c8]Rani S. Ghaida, Yasmine Badr, Puneet Gupta:
Pattern-restricted design at 10nm and beyond. ICCD 2014: 308-310 - 2013
- [j3]Rani S. Ghaida, Kanak B. Agarwal, Sani R. Nassif, Xin Yuan, Lars Liebmann, Puneet Gupta:
Layout Decomposition and Legalization for Double-Patterning Technology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(2): 202-215 (2013) - [c7]Rani S. Ghaida, Puneet Gupta:
Role of design in multiple patterning: technology development, design enablement and process control. DATE 2013: 314-319 - 2012
- [b1]Rani S. Ghaida:
Design Enablement and Design-Centric Assessment of Future Semiconductor Technologies. University of California, Los Angeles, USA, 2012 - [j2]Rani S. Ghaida, Puneet Gupta:
DRE: A Framework for Early Co-Evaluation of Design Rules, Technology Choices, and Layout Methodologies. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(9): 1379-1392 (2012) - [c6]Rani S. Ghaida, Tanaya Sahu, Parag Kulkarni, Puneet Gupta:
A methodology for the early exploration of design rules for multiple-patterning technologies. ICCAD 2012: 50-56 - [c5]Rani S. Ghaida, Kanak B. Agarwal, Sani R. Nassif, Xin Yuan, Lars W. Liebmann, Puneet Gupta:
O(n) layout-coloring for multiple-patterning lithography and conflict-removal using compaction. ICICDT 2012: 1-4 - 2011
- [c4]Rani S. Ghaida, Kanak B. Agarwal, Sani R. Nassif, Xin Yuan, Lars Liebmann, Puneet Gupta:
A framework for double patterning-enabled design. ICCAD 2011: 14-20 - 2010
- [c3]Tuck-Boon Chan, Rani S. Ghaida, Puneet Gupta:
Electrical Modeling of Lithographic Imperfections. VLSI Design 2010: 423-428
2000 – 2009
- 2009
- [j1]Rani S. Ghaida, Payman Zarkesh-Ha:
A Layout Sensitivity Model for Estimating Electromigration-vulnerable Narrow Interconnects. J. Electron. Test. 25(1): 67-77 (2009) - [c2]Rani S. Ghaida, Puneet Gupta:
A framework for early and systematic evaluation of design rules. ICCAD 2009: 615-622 - 2007
- [c1]Rani S. Ghaida, Payman Zarkesh-Ha:
Estimation of Electromigration-Aggravating Narrow Interconnects Using a Layout Sensitivity Model. DFT 2007: 59-67
Coauthor Index
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