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ORCIDJerzy J. Dabrowski
Person information
- unicode name: Jerzy J. Dąbrowski
- affiliation: Linkoping University, Department of Electrical Engineering, Sweden
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2020 – today
- 2020
[j10]Shakeel Ahmad, Jerzy J. Dabrowski:
One-Bit ΣΔ-Encoded Stimulus Generation for On-Chip ADC Test. J. Circuits Syst. Comput. 29(15): 2050245:1-2050245:25 (2020)
2010 – 2019
- 2019
- [j9]Shakeel Ahmad
, Jerzy J. Dabrowski:
Design of Two-Tone RF Generator for On-Chip IP3/IP2 Test. J. Electron. Test. 35(1): 77-85 (2019) - 2016
- [j8]Fahad Qazi, Quoc-Tai Duong, Jerzy J. Dabrowski:
Tunable selective receiver front end with impedance transformation filtering. Int. J. Circuit Theory Appl. 44(5): 1071-1093 (2016) - 2015
- [j7]Fahad Qazi, Jerzy J. Dabrowski:
Passive SC Sigma Delta Modulators Revisited: Analysis and Design Study. IEEE J. Emerg. Sel. Topics Circuits Syst. 5(4): 624-637 (2015) - [j6]Rashad Ramzan, Jerzy J. Dabrowski:
RF calibration of on-chip DfT chain by DC stimuli and statistical multivariate regression technique. Integr. 49: 14-21 (2015) - [j5]Fahad Quiz, Quoc-Tai Duong, Jerzy J. Dabrowski:
Two-Stage Highly Selective Receiver Front End Based on Impedance Transformation Filtering. IEEE Trans. Circuits Syst. II Express Briefs 62-II(5): 421-425 (2015) - [c23]Fahad Qazi, Jerzy J. Dabrowski:
Clock phase imbalance and phase noise in RF N-path filters. ECCTD 2015: 1-4 - 2013
- [c22]Quoc-Tai Duong, Jerzy J. Dabrowski:
Focused calibration for advanced RF test with embedded RF detectors. ECCTD 2013: 1-4 - [c21]Fahad Qazi, Quoc-Tai Duong, Jerzy J. Dabrowski:
Blocker and image reject low-IF frontend. ECCTD 2013: 1-4 - [c20]Quoc-Tai Duong, Jerzy J. Dabrowski, Atila Alvandpour:
Highly linear open-loop output driver design for high speed capacitive DACs. NORCHIP 2013: 1-4 - 2012
- [c19]Quoc-Tai Duong, Jerzy J. Dabrowski:
Wideband RF detector design for high performance on-chip test. NORCHIP 2012: 1-4 - 2011
- [c18]Shakeel Ahmad, Jerzy J. Dabrowski:
On-chip spectral test for high-speed ADCs by ΣΔ technique. ECCTD 2011: 661-664 - [c17]Quoc-Tai Duong, Jerzy J. Dabrowski:
Low noise transconductance amplifier design for continuous-time ΣΔ wideband frontend. ECCTD 2011: 825-828 - 2010
- [j4]Rashad Ramzan, N. Ahsan, Jerzy J. Dabrowski:
On-Chip Stimulus Generator for Gain, Linearity, and Blocking Profile Test of Wideband RF Front Ends. IEEE Trans. Instrum. Meas. 59(11): 2870-2876 (2010) - [j3]Jerzy J. Dabrowski, Rashad Ramzan:
Built-in Loopback Test for IC RF Transceivers. IEEE Trans. Very Large Scale Integr. Syst. 18(6): 933-946 (2010) - [c16]Shakeel Ahmad, Kaveh Azizi, Iman Esmaeil Zadeh, Jerzy J. Dabrowski:
Two-tone PLL for on-chip IP3 test. ISCAS 2010: 3549-3552
2000 – 2009
- 2009
- [c15]Shakeel Ahmad, Jerzy J. Dabrowski:
On-chip stimuli generation for ADC dynamic test by ΣΔ technique. ECCTD 2009: 105-108 - 2007
- [c14]Jerzy J. Dabrowski, Rashad Ramzan:
Interactive presentation: Boosting SER test for RF transceivers by simple DSP technique. DATE 2007: 719-724 - [c13]Stefan Back Andersson, Rashad Ramzan, Jerzy J. Dabrowski, Christer Svensson:
Multiband direct RF-sampling receiver front-end for WLAN in 0.13 μm CMOS. ECCTD 2007: 168-171 - [c12]Rashad Ramzan, Stefan Back Andersson, Jerzy J. Dabrowski, Christer Svensson:
A 1.4V 25mW Inductorless Wideband LNA in 0.13μm CMOS. ISSCC 2007: 424-613 - 2006
- [c11]Stefan Back Andersson, Jerzy J. Dabrowski, Christer Svensson, J. Konopacki:
SC filter for RF down conversion with wideband image rejection. ISCAS 2006 - [c10]Rashad Ramzan, Lei Zou, Jerzy J. Dabrowski:
LNA design for on-chip RF test. ISCAS 2006 - 2005
- [j2]Darius Jakonis, Kalle Folkesson, Jerzy J. Dabrowski, Patrik Eriksson, Christer Svensson:
A 2.4-GHz RF sampling receiver front-end in 0.18-μm CMOS. IEEE J. Solid State Circuits 40(6): 1265-1277 (2005) - [c9]Jerzy J. Dabrowski, Javier Gonzalez Bayon:
Techniques for sensitizing RF path under SER test. ISCAS (5) 2005: 4843-4846 - 2004
- [c8]Jerzy J. Dabrowski, Javier Gonzalez Bayon:
Mixed Loopback BiST for RF Digital Transceivers. DFT 2004: 220-228 - [c7]Jerzy J. Dabrowski:
Fault modeling of RF blocks based on noise analysis. ISCAS (1) 2004: 513-516 - 2003
- [c6]Jerzy J. Dabrowski:
BiST Model for IC RF-Transceiver Front-End. DFT 2003: 295-302 - [c5]Jerzy J. Dabrowski:
Lookback BiST for RF front-ends in digital transceivers. SoC 2003: 143-146 - 2002
- [c4]Jerzy J. Dabrowski:
Efficient post-layout timing verification via RLC trees and explicit PWL timing integration. ICECS 2002: 689-692 - 2000
- [c3]Jerzy J. Dabrowski:
Efficient interconnect timing analysis via piecewise linear technique. ISCAS 2000: 469-472
1990 – 1999
- 1999
- [c2]Jerzy J. Dabrowski, Andrzej Pulka:
Experiences with Modeling of Analog and Mixed A/D Systems Based on PWL Technique. DATE 1999: 790-791 - 1995
- [c1]Jerzy J. Dabrowski:
Functional-level analog macromodeling with piecewise linear signals. EURO-DAC 1995: 222-227 - 1992
- [j1]Jerzy J. Dabrowski:
Efficient timing verification via mixed-mode technique. Microprocess. Microprogramming 34(1-5): 183-186 (1992)
Coauthor Index
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last updated on 2023-10-01 22:24 CEST by the dblp team
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