![](https://dblp.org/img/logo.ua.320x120.png)
![](https://dblp.org/img/dropdown.dark.16x16.png)
![](https://dblp.org/img/peace.dark.16x16.png)
Остановите войну!
for scientists:
![search dblp search dblp](https://dblp.org/img/search.dark.16x16.png)
![search dblp](https://dblp.org/img/search.dark.16x16.png)
default search action
Hiroki Matsutani
Person information
Refine list
![note](https://dblp.org/img/note-mark.dark.12x12.png)
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
2020 – today
- 2024
- [j49]Shin Morishima
, Hiroki Matsutani
:
An Efficient Distributed Reinforcement Learning Architecture for Long-Haul Communication Between Actors and Learner. IEEE Access 12: 71479-71491 (2024) - [j48]Kazuki Sunaga, Takeya Yamada, Hiroki Matsutani:
A Sequential Approach to Detect Drifts and Retrain Neural Networks on Resource-Limited Edge Devices. IEICE Trans. Inf. Syst. 107(6): 741-750 (2024) - [j47]Yuto Hoshino, Hiroki Kawakami, Hiroki Matsutani:
Federated Learning of Neural ODE Models with Different Iteration Counts. IEICE Trans. Inf. Syst. 107(6): 781-791 (2024) - [j46]Keisuke Sugiura
, Hiroki Matsutani
:
An Integrated FPGA Accelerator for Deep Learning-Based 2D/3D Path Planning. IEEE Trans. Computers 73(6): 1442-1456 (2024) - [c125]Kazuki Sunaga, Keisuke Sugiura, Hiroki Matsutani:
An FPGA-Based Accelerator for Graph Embedding using Sequential Training Algorithm. IPDPS (Workshops) 2024: 148-154 - [c124]Yujiro Yahata, Keisuke Sugiura, Hiroki Matsutani:
A Scalable Secure Fault Tolerant Aggregation for P2P Federated Learning. IPDPS (Workshops) 2024: 222-231 - [i19]Ikumi Okubo, Keisuke Sugiura, Hiroki Matsutani:
A Cost-Efficient FPGA Implementation of Tiny Transformer Model using Neural ODE. CoRR abs/2401.02721 (2024) - [i18]Keisuke Sugiura, Hiroki Matsutani:
FPGA-Accelerated Correspondence-free Point Cloud Registration with PointNet Features. CoRR abs/2404.01237 (2024) - 2023
- [j45]Ryota Yasudo
, Koji Nakano
, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano:
Designing low-diameter interconnection networks with multi-ported host-switch graphs. Concurr. Comput. Pract. Exp. 35(11) (2023) - [j44]Hiroki Kawakami, Hirohisa Watanabe, Keisuke Sugiura, Hiroki Matsutani:
A Low-Cost Neural ODE with Depthwise Separable Convolution for Edge Domain Adaptation on FPGAs. IEICE Trans. Inf. Syst. 106(7): 1186-1197 (2023) - [j43]Kenji Nemoto, Hiroki Matsutani:
A Lightweight Reinforcement Learning Based Packet Routing Method Using Online Sequential Learning. IEICE Trans. Inf. Syst. 106(11): 1796-1807 (2023) - [j42]Kazuki Sunaga
, Masaaki Kondo
, Hiroki Matsutani
:
Addressing the Gap Between Training Data and Deployed Environment by On-Device Learning. IEEE Micro 43(6): 66-73 (2023) - [c123]Naoki Shibahara, Michihiro Koibuchi, Hiroki Matsutani:
Performance Improvement of Federated Learning Server using Smart NIC. CANDARW 2023: 165-171 - [c122]Ikumi Okubo, Keisuke Sugiura, Hiroki Kawakami, Hiroki Matsutani:
A Lightweight Transformer Model using Neural ODE for FPGAs. IPDPS Workshops 2023: 105-112 - [c121]Mizuki Yasuda, Keisuke Sugiura, Ryuto Kojima, Hiroki Matsutani:
An Edge-Server Partitioning Method for 3D LiDAR SLAM on FPGAs. IPDPS Workshops 2023: 113-120 - [c120]Takeya Yamada, Hiroki Matsutani:
A Lightweight Concept Drift Detection Method for On-Device Learning on Resource-Limited Edge Devices. IPDPS Workshops 2023: 761-768 - [c119]Keisuke Sugiura, Hiroki Matsutani:
An Efficient Accelerator for Deep Learning-based Point Cloud Registration on FPGAs. PDP 2023: 68-75 - [i17]Keisuke Sugiura, Hiroki Matsutani:
An Integrated FPGA Accelerator for Deep Learning-based 2D/3D Path Planning. CoRR abs/2306.17625 (2023) - [i16]Naoki Shibahara, Michihiro Koibuchi, Hiroki Matsutani:
A Case for Offloading Federated Learning Server on Smart NIC. CoRR abs/2307.06561 (2023) - [i15]Kazuki Sunaga, Keisuke Sugiura, Hiroki Matsutani:
An FPGA-Based Accelerator for Graph Embedding using Sequential Training Algorithm. CoRR abs/2312.15138 (2023) - 2022
- [j41]Keisuke Sugiura
, Hiroki Matsutani
:
A Universal LiDAR SLAM Accelerator System on Low-Cost FPGA. IEEE Access 10: 26931-26947 (2022) - [j40]Mineto Tsukada, Hiroki Matsutani:
An Overflow/Underflow-Free Fixed-Point Bit-Width Optimization Method for OS-ELM Digital Circuit. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 105-A(3): 437-447 (2022) - [j39]Yoshiya Shikama
, Ryuta Kawano
, Hiroki Matsutani, Hideharu Amano, Yusuke Nagasaka, Naoto Fukumoto
, Michihiro Koibuchi:
A traffic-aware memory-cube network using bypassing. Microprocess. Microsystems 90: 104471 (2022) - [c118]Keisuke Sugiura, Hiroki Matsutani:
P3Net: PointNet-based Path Planning on FPGA. FPT 2022: 1-9 - [c117]Man Wu
, Hiroki Matsutani, Masaaki Kondo:
ONLAD-IDS: ONLAD-Based Intrusion Detection System Using SmartNIC. HPCC/DSS/SmartCity/DependSys 2022: 546-553 - [c116]Yuto Hoshino, Hiroki Kawakami, Hiroki Matsutani:
Communication Size Reduction of Federated Learning based on Neural ODE Model. CANDARW 2022: 55-61 - [c115]Kenji Nemoto, Hiroki Matsutani:
A Packet Routing using Lightweight Reinforcement Learning Based on Online Sequential Learning. CANDARW 2022: 76-82 - [c114]Ryuta Kawano, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Dynamic Routing Reconfiguration for Low-Latency and Deadlock-Free Interconnection Networks. CANDAR 2022: 117-123 - [c113]Masaki Furukawa, Hiroki Matsutani:
Accelerating Distributed Deep Reinforcement Learning by In-Network Experience Sampling. PDP 2022: 75-82 - [c112]Hiroki Kawakami, Hirohisa Watanabe, Keisuke Sugiura, Hiroki Matsutani:
dsODENet: Neural ODE and Depthwise Separable Convolution for Domain Adaptation on FPGAs. PDP 2022: 152-156 - [i14]Hiroki Matsutani, Mineto Tsukada, Masaaki Kondo:
On-Device Learning: A Neural Network Based Field-Trainable Edge AI. CoRR abs/2203.01077 (2022) - [i13]Keisuke Sugiura, Hiroki Matsutani:
An Efficient Accelerator for Deep Learning-based Point Cloud Registration on FPGAs. CoRR abs/2203.05763 (2022) - [i12]Yuto Hoshino, Hiroki Kawakami, Hiroki Matsutani:
Communication Size Reduction of Federated Learning based on Neural ODE Model. CoRR abs/2208.09478 (2022) - [i11]Takeya Yamada, Hiroki Matsutani:
A Sequential Concept Drift Detection Method for On-Device Learning on Low-End Edge Devices. CoRR abs/2212.09637 (2022) - 2021
- [j38]Rei Ito, Mineto Tsukada
, Hiroki Matsutani
:
An On-Device Federated Learning Approach for Cooperative Model Update Between Edge Devices. IEEE Access 9: 92986-92998 (2021) - [j37]Takuya Sakuma, Hiroki Matsutani:
An Area-Efficient Recurrent Neural Network Core for Unsupervised Time-Series Anomaly Detection. IEICE Trans. Electron. 104-C(6): 247-256 (2021) - [j36]Keisuke Sugiura, Hiroki Matsutani:
An FPGA Acceleration and Optimization Techniques for 2D LiDAR SLAM Algorithm. IEICE Trans. Inf. Syst. 104-D(6): 789-800 (2021) - [j35]Tomoya Itsubo, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani:
An FPGA-Based Optimizer Design for Distributed Deep Learning with Multiple GPUs. IEICE Trans. Inf. Syst. 104-D(12): 2057-2067 (2021) - [j34]Masaki Furukawa, Tomoya Itsubo, Hiroki Matsutani:
An In-Network Parameter Aggregation using DPDK for Multi-GPU Deep Learning. Int. J. Netw. Comput. 11(2): 516-532 (2021) - [c111]Ryuta Kawano
, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
GPU Parallelization of All-Pairs-Shortest-Path Algorithm in Low-Degree Unweighted Regular Graph. ACIT 2021: 51-55 - [c110]Keisuke Sugiura, Hiroki Matsutani:
A unified accelerator design for LiDAR SLAM algorithms for low-end FPGAs. FPT 2021: 1-9 - [c109]Hirohisa Watanabe, Hiroki Matsutani:
Accelerating ODE-Based Neural Networks on Low-Cost FPGAs. IPDPS Workshops 2021: 88-95 - [c108]Hirohisa Watanabe, Mineto Tsukada, Hiroki Matsutani:
An FPGA-Based On-Device Reinforcement Learning Approach using Online Sequential Learning. IPDPS Workshops 2021: 96-103 - [c107]Yoshiya Shikama, Ryuta Kawano
, Hiroki Matsutani, Hideharu Amano, Yusuke Nagasaka, Naoto Fukumoto, Michihiro Koibuchi:
Low-Latency Low-Energy Memory-Cube Networks using Dual-Voltage Datapaths. PDP 2021: 143-147 - [i10]Keisuke Sugiura, Hiroki Matsutani:
Particle Filter-based vs. Graph-based: SLAM Acceleration on Low-end FPGAs. CoRR abs/2103.09523 (2021) - [i9]Mineto Tsukada, Hiroki Matsutani:
An Overflow/Underflow-Free Fixed-Point Bit-Width Optimization Method for OS-ELM Digital Circuit. CoRR abs/2103.09791 (2021) - [i8]Hiroki Kawakami, Hirohisa Watanabe, Keisuke Sugiura, Hiroki Matsutani:
A Low-Cost Neural ODE with Depthwise Separable Convolution for Edge Domain Adaptation on FPGAs. CoRR abs/2107.12824 (2021) - [i7]Masaki Furukawa, Hiroki Matsutani:
A DPDK-Based Acceleration Method for Experience Sampling of Distributed Reinforcement Learning. CoRR abs/2110.13506 (2021) - 2020
- [j33]Ryuta Kawano
, Ryota Yasudo
, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
A Generalized Theory Based on the Turn Model for Deadlock-Free Irregular Networks. IEICE Trans. Inf. Syst. 103-D(1): 101-110 (2020) - [j32]Shin Morishima, Hiroki Matsutani:
In-GPU Cache for Acceleration of Anomaly Detection in Blockchain. IEICE Trans. Inf. Syst. 103-D(8): 1814-1824 (2020) - [j31]Ryuta Kawano
, Ryota Yasudo
, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Traffic-Independent Multi-Path Routing for High-Throughput Data Center Networks. IEICE Trans. Inf. Syst. 103-D(12): 2471-2479 (2020) - [j30]Mineto Tsukada
, Masaaki Kondo
, Hiroki Matsutani
:
A Neural Network-Based On-Device Learning Anomaly Detector for Edge Devices. IEEE Trans. Computers 69(7): 1027-1044 (2020) - [c106]Takuya Sakuma, Hiroki Matsutani:
An Area-Efficient Implementation of Recurrent Neural Network Core for Unsupervised Anomaly Detection. COOL CHIPS 2020: 1-3 - [c105]Tokio Kibata, Mineto Tsukada, Hiroki Matsutani:
An Edge Attribute-Wise Partitioning and Distributed Processing of R-GCN Using GPUs. Euro-Par Workshops 2020: 122-134 - [c104]Ryuta Kawano
, Hiroki Matsutani, Hideharu Amano:
Layout-Oriented Low-Diameter Topology for HPC Interconnection Networks. CANDAR (Workshops) 2020: 93-99 - [c103]Masaki Furukawa, Tomoya Itsubo, Hiroki Matsutani:
An In-Network Parameter Aggregation using DPDK for Multi-GPU Deep Learning. CANDAR 2020: 108-114 - [c102]Yang Qin, Hiroki Matsutani, Masaaki Kondo:
A Selective Model Aggregation Approach in Federated Learning for Online Anomaly Detection. iThings/GreenCom/CPSCom/SmartData/Cybermatics 2020: 684-691 - [c101]Hiroki Oikawa, Tomoya Nishida, Ryuichi Sakamoto, Hiroki Matsutani, Masaaki Kondo:
Fast Semi-Supervised Anomaly Detection of Drivers' Behavior using Online Sequential Extreme Learning Machine. ITSC 2020: 1-8 - [c100]Tomoya Itsubo, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani:
Accelerating Deep Learning using Multiple GPUs and FPGA-Based 10GbE Switch. PDP 2020: 102-109 - [i6]Rei Ito, Mineto Tsukada, Hiroki Matsutani:
An On-Device Federated Learning Approach for Cooperative Anomaly Detection. CoRR abs/2002.12301 (2020) - [i5]Hirohisa Watanabe, Mineto Tsukada, Hiroki Matsutani:
An FPGA-Based On-Device Reinforcement Learning Approach using Online Sequential Learning. CoRR abs/2005.04646 (2020) - [i4]Keisuke Sugiura, Hiroki Matsutani:
An FPGA Acceleration and Optimization Techniques for 2D LiDAR SLAM Algorithm. CoRR abs/2006.01050 (2020) - [i3]Hirohisa Watanabe, Hiroki Matsutani:
Accelerating ODE-Based Neural Networks on Low-Cost FPGAs. CoRR abs/2012.15465 (2020)
2010 – 2019
- 2019
- [j29]Takuma Iwata, Kohei Nakamura, Yuta Tokusashi, Hiroki Matsutani:
An FPGA-Based Change-Point Detection for 10Gbps Packet Stream. IEICE Trans. Inf. Syst. 102-D(12): 2366-2376 (2019) - [j28]Ryota Yasudo
, Michihiro Koibuchi, Koji Nakano
, Hiroki Matsutani, Hideharu Amano:
Designing High-Performance Interconnection Networks with Host-Switch Graphs. IEEE Trans. Parallel Distributed Syst. 30(2): 315-330 (2019) - [c99]Tomoya Itsubo, Mineto Tsukada, Hiroki Matsutani:
Performance and Cost Evaluations of Online Sequential Learning and Unsupervised Anomaly Detection Core. COOL CHIPS 2019: 1-3 - [c98]Yuta Tokusashi, Hiroki Matsutani, Hideharu Amano:
Key-value Store Chip Design for Low Power Consumption. COOL CHIPS 2019: 1-3 - [c97]Rei Ito, Mineto Tsukada, Masaaki Kondo, Hiroki Matsutani:
An Adaptive Abnormal Behavior Detection using Online Sequential Learning. CSE/EUC 2019: 436-440 - [c96]Michihiro Koibuchi, Lambert Leong, Tomohiro Totoki, Naoya Niwa
, Hiroki Matsutani, Hideharu Amano, Henri Casanova:
Sparse 3-D NoCs with Inductive Coupling. DAC 2019: 49 - [c95]Ryuta Kawano
, Hiroki Matsutani, Hideharu Amano:
Deadlock-Free Layered Routing for Infiniband Networks. CANDAR Workshops 2019: 84-90 - [i2]Mineto Tsukada, Masaaki Kondo, Hiroki Matsutani:
A Neural Network Based On-device Learning Anomaly Detector for Edge Devices. CoRR abs/1907.10147 (2019) - 2018
- [j27]Yuma Sakakibara, Shin Morishima, Kohei Nakamura, Hiroki Matsutani:
A Hardware-Based Caching System on FPGA NIC for Blockchain. IEICE Trans. Inf. Syst. 101-D(5): 1350-1360 (2018) - [j26]Koya Mitsuzuka, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani:
Proxy Responses by FPGA-Based Switch for MapReduce Stragglers. IEICE Trans. Inf. Syst. 101-D(9): 2258-2268 (2018) - [j25]Akio Nomura, Yusuke Matsushita, Junichiro Kadomoto, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano:
Escalator Network for a 3D Chip Stack with Inductive Coupling ThruChip Interface. Int. J. Netw. Comput. 8(1): 124-139 (2018) - [c94]Takuma Iwata, Kohei Nakamura, Yuta Tokusashi, Hiroki Matsutani:
Accelerating Online Change-Point Detection Algorithm Using 10 GbE FPGA NIC. Euro-Par Workshops 2018: 506-517 - [c93]Mineto Tsukada, Masaaki Kondo, Hiroki Matsutani:
OS-ELM-FPGA: An FPGA-Based Online Sequential Unsupervised Anomaly Detector. Euro-Par Workshops 2018: 518-529 - [c92]Koya Mitsuzuka, Yuta Tokusashi, Hiroki Matsutani:
MultiMQC: A Multilevel Message Queuing Cache Combining In-NIC and In-Kernel Memories. FPT 2018: 134-141 - [c91]Ryuta Kawano
, Ryota Yasudo
, Hiroki Matsutani, Hideharu Amano:
k-Optimized Path Routing for High-Throughput Data Center Networks. CANDAR 2018: 99-105 - [c90]Naoya Niwa
, Tomohiro Totoki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
An Trace-Driven Performance Prediction Method for Exploring NoC Design Optimization. CANDAR Workshops 2018: 182-185 - [c89]Yuma Sakakibara, Yuta Tokusashi, Shin Morishima, Hiroki Matsutani:
Accelerating Blockchain Transfer System Using FPGA-Based NIC. ISPA/IUCC/BDCloud/SocialCom/SustainCom 2018: 171-178 - [c88]Shin Morishima, Hiroki Matsutani:
Acceleration of Anomaly Detection in Blockchain Using In-GPU Cache. ISPA/IUCC/BDCloud/SocialCom/SustainCom 2018: 244-251 - [c87]Kaho Okuyama, Yuta Tokusashi, Takuma Iwata, Mineto Tsukada, Kazumasa Kishiki, Hiroki Matsutani:
Network Optimizations on Prediction Server with Multiple Predictors. ISPA/IUCC/BDCloud/SocialCom/SustainCom 2018: 1044-1045 - [c86]Akram Ben Ahmed
, Hayate Okuhara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Adaptive Body Bias Control Scheme for Ultra Low-Power Network-on-Chip Systems. MCSoC 2018: 146-153 - [c85]Truong Thao Nguyen
, Hiroki Matsutani, Michihiro Koibuchi:
Low-Reliable Low-Latency Networks Optimized for HPC Parallel Applications. NCA 2018: 1-10 - [c84]Akram Ben Ahmed
, Daichi Fujiki
, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
AxNoC: Low-power Approximate Network-on-Chips using Critical-Path Isolation. NOCS 2018: 6:1-6:8 - [c83]Shin Morishima, Hiroki Matsutani:
Accelerating Blockchain Search of Full Nodes Using GPUs. PDP 2018: 244-248 - [c82]Yuta Tokusashi, Hiroki Matsutani, Noa Zilberman
:
LaKe: The Power of In-Network Computing. ReConFig 2018: 1-8 - [c81]Terrence S. T. Mak, Hiroki Matsutani, Partha Pratim Pande:
Special session on bringing cores closer together: The wireless revolution in on-chip communication. VTS 2018: 1 - [i1]Yuta Tokusashi, Hiroki Matsutani, Noa Zilberman
:
LaKe: An Energy Efficient, Low Latency, Accelerated Key-Value Store. CoRR abs/1805.11344 (2018) - 2017
- [j24]Ryuta Kawano
, Hiroshi Nakahara, Seiichi Tade, Ikki Fujiwara
, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
A Novel Channel Assignment Method to Ensure Deadlock-Freedom for Deterministic Routing. IEICE Trans. Inf. Syst. 100-D(8): 1798-1806 (2017) - [j23]Ryuta Kawano
, Hiroshi Nakahara, Ikki Fujiwara
, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
A Layout-Oriented Routing Method for Low-Latency HPC Networks. IEICE Trans. Inf. Syst. 100-D(12): 2796-2807 (2017) - [j22]Shin Morishima, Hiroki Matsutani:
High-Performance with an In-GPU Graph Database Cache. IT Prof. 19(6): 58-64 (2017) - [j21]Yuta Tokusashi, Hiroki Matsutani:
Multilevel NoSQL Cache Combining In-NIC and In-Kernel Approaches. IEEE Micro 37(5): 44-51 (2017) - [j20]Ryota Yasudo
, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tadao Nakamura:
Scalable Networks-on-Chip with Elastic Links Demarcated by Decentralized Routers. IEEE Trans. Computers 66(4): 702-716 (2017) - [c80]Michihiro Koibuchi, Tomohiro Totoki, Hiroki Matsutani, Hideharu Amano, Fabien Chaix, Ikki Fujiwara
, Henri Casanova:
A Case for Uni-directional Network Topologies in Large-Scale Clusters. CLUSTER 2017: 178-187 - [c79]Koya Mitsuzuka, Ami Hayashi, Michihiro Koibuchi, Hideharu Amano, Hiroki Matsutani:
In-switch approximate processing: Delayed tasks management for MapReduce applications. FPL 2017: 1-4 - [c78]Yuma Sakakibara, Kohei Nakamura, Hiroki Matsutani:
An FPGA NIC Based Hardware Caching for Blockchain. HEART 2017: 1:1-1:6 - [c77]Shin Morishima, Masahiro Okazaki, Hiroki Matsutani:
A Case for Remote GPUs over 10GbE Network for VR Applications. HEART 2017: 19:1-19:6 - [c76]Daichi Fujiki
, Kiyo Ishii, Ikki Fujiwara
, Hiroki Matsutani, Hideharu Amano, Henri Casanova, Michihiro Koibuchi:
High-Bandwidth Low-Latency Approximate Interconnection Networks. HPCA 2017: 469-480 - [c75]Yao Hu, Hiroaki Hara, Ikki Fujiwara
, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi:
Towards Tightly-coupled Datacenter with Free-space Optical Links. ICCBDC 2017: 33-39 - [c74]Ryuta Kawano
, Ryota Yasudo
, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
HiRy: An Advanced Theory on Design of Deadlock-Free Adaptive Routing for Arbitrary Topologies. ICPADS 2017: 664-673 - [c73]Ryota Yasudo
, Michihiro Koibuchi, Koji Nakano
, Hiroki Matsutani, Hideharu Amano:
Order/Radix Problem: Towards Low End-to-End Latency Interconnection Networks. ICPP 2017: 322-331 - [c72]Hideharu Amano, Tadahiro Kuroda, Hiroshi Nakamura
, Kimiyoshi Usami, Masaaki Kondo, Hiroki Matsutani, Mitaro Namiki:
Building block multi-chip systems using inductive coupling through chip interface. ISOCC 2017: 152-154 - [c71]Hiroshi Nakahara, Ryota Yasudo
, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi:
3D Layout of Spidergon, Flattened Butterfly and Dragonfly on a Chip Stack with Inductive Coupling Through Chip Interface. ISPAN-FCST-ISCC 2017: 52-59 - [c70]Ami Hayashi, Hiroki Matsutani:
An FPGA-based In-NIC Cache Approach for Lazy Learning Outlier Filtering. PDP 2017: 15-22 - [e1]Axel Jantsch, Hiroki Matsutani, Zhonghai Lu, Ümit Y. Ogras:
Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2017, Seoul, Republic of Korea, October 19 - 20, 2017. ACM 2017, ISBN 978-1-4503-4984-0 [contents] - 2016
- [j19]Michihiro Koibuchi, Ikki Fujiwara
, Kiyo Ishii
, Shu Namiki
, Fabien Chaix, Hiroki Matsutani, Hideharu Amano, Tomohiro Kudoh:
Optical network technologies for HPC: computer-architects point of view. IEICE Electron. Express 13(6): 20152007 (2016) - [j18]Akram Ben Ahmed
, Hiroki Matsutani, Michihiro Koibuchi, Kimiyoshi Usami, Hideharu Amano:
Multi-Voltage Variable Pipeline Routers with the Same Clock Frequency for Low-Power Network-on-Chips Systems. IEICE Trans. Electron. 99-C(8): 909-917 (2016) - [j17]Hiroshi Nakahara, Tomoya Ozaki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Novel Chip Stacking Methods to Extend Both Horizontally and Vertically for Many-Core Architectures with ThrouChip Interface. IEICE Trans. Inf. Syst. 99-D(12): 2871-2880 (2016) - [j16]Takahiro Kagami, Hiroki Matsutani, Michihiro Koibuchi, Yasuhiro Take, Tadahiro Kuroda, Hideharu Amano:
Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces. IEEE Trans. Very Large Scale Integr. Syst. 24(2): 493-506 (2016) - [c69]Ryuta Kawano
, Hiroshi Nakahara, Seiichi Tade, Ikki Fujiwara
, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
ACRO: Assignment of channels in reverse order to make arbitrary routing deadlock-free. ICIS 2016: 1-6 - [c68]Kohei Nakamura, Ami Hayashi, Hiroki Matsutani:
An FPGA-based low-latency network processing for spark streaming. IEEE BigData 2016: 2410-2415 - [c67]Shin Morishima, Hiroki Matsutani:
Distributed In-GPU Data Cache for Document-Oriented Data Store via PCIe over 10 Gbit Ethernet. Euro-Par Workshops 2016: 41-55 - [c66]Yuta Tokusashi, Hiroki Matsutani:
NOSQL hardware appliance with multiple data structure. Hot Chips Symposium 2016: 1 - [c65]Yuta Tokusashi, Hiroki Matsutani:
A Multilevel NOSQL Cache Design Combining In-NIC and In-Kernel Caches. Hot Interconnects 2016: 60-67 - [c64]Ryuta Kawano, Hiroshi Nakahara, Ikki Fujiwara, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
LOREN: A Scalable Routing Method for Layout-Conscious Random Topologies. CANDAR 2016: 9-18 - [c63]Akio Nomura, Hiroki Matsutani, Tadahiro Kuroda, Junichiro Kadomoto, Yusuke Matsushita, Hideharu Amano:
Vertical Packet Switching Elevator Network Using Inductive Coupling ThruChip Interface. CANDAR 2016: 195-201 - [c62]Yasuhiro Ohno, Shin Morishima, Hiroki Matsutani:
Accelerating Spark RDD Operations with Local and Remote GPU Devices. ICPADS 2016: 791-799 - [c61]Koji Nakano
, Daisuke Takafuji, Satoshi Fujita, Hiroki Matsutani, Ikki Fujiwara
, Michihiro Koibuchi:
Randomly Optimized Grid Graph for Low-Latency Interconnection Networks. ICPP 2016: 340-349 - [c60]Daichi Fujiki
, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Randomizing Packet Memory Networks for Low-Latency Processor-Memory Communication. PDP 2016: 168-175 - [c59]Akihiko Hamada, Hiroki Matsutani:
Design and implementation of hardware cache mechanism and NIC for column-oriented databases. ReConFig 2016: 1-6 - [c58]Partha Pratim Pande, Sudeep Pasricha, Hiroki Matsutani:
The Future of NoCs: New Technologies and Architectures. VLSID 2016: 53-55 - 2015
- [j15]Ami Hayashi, Yuta Tokusashi, Hiroki Matsutani:
A Line Rate Outlier Filtering FPGA NIC using 10GbE Interface. SIGARCH Comput. Archit. News 43(4): 22-27 (2015) - [j14]Ikki Fujiwara
, Michihiro Koibuchi, Hiroki Matsutani, Henri Casanova
:
Swap-And-Randomize: A Method for Building Low-Latency HPC Interconnects. IEEE Trans. Parallel Distributed Syst. 26(7): 2051-2060 (2015) - [c57]Seiichi Tade, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi:
A metamorphotic Network-on-Chip for various types of parallel applications. ASAP 2015: 98-105 - [c56]Ikki Fujiwara
, Michihiro Koibuchi, Tomoya Ozaki, Hiroki Matsutani, Henri Casanova:
Augmenting low-latency HPC network with free-space optical links. HPCA 2015: 390-401 - [c55]Hiroshi Nakahara, Tomoya Ozaki, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Expandable Chip Stacking Method for Many-core Architectures Consisting of Tiny Chips. MCSoC 2015: 41-48 - [c54]Akio Nomura, Yu Fujita, Hiroki Matsutani, Hideharu Amano:
3D Shared Bus Architecture Using Inductive Coupling Interconnect. MCSoC 2015: 259-266 - [c53]Ryota Yasudo
, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tadao Nakamura:
On-Chip Decentralized Routers with Balanced Pipelines for Avoiding Interconnect Bottleneck. NOCS 2015: 16:1-16:8 - [c52]Ryuta Kawano
, Seiichi Tade, Ikki Fujiwara
, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi:
Optimized Core-Links for Low-Latency NoCs. PDP 2015: 172-176 - [c51]Shin Morishima, Hiroki Matsutani:
Performance Evaluations of Document-Oriented Databases Using GPU and Cache Structure. TrustCom/BigDataSE/ISPA (3) 2015: 108-115 - 2014
- [j13]Hao Zhang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Dynamic Power Consumption Optimization for Inductive-Coupling based Wireless 3D NoCs. IPSJ Trans. Syst. LSI Des. Methodol. 7: 27-36 (2014) - [j12]Shin Morishima, Hiroki Matsutani:
Performance Evaluations of Graph Database using CUDA and OpenMP Compatible Libraries. SIGARCH Comput. Archit. News 42(4): 75-80 (2014) - [j11]Yasuhiro Take, Hiroki Matsutani, Daisuke Sasaki, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano:
3D NoC with Inductive-Coupling Links for Building-Block SiPs. IEEE Trans. Computers 63(3): 748-763 (2014) - [c50]Hiroki Matsutani, Michihiro Koibuchi, Ikki Fujiwara, Takahiro Kagami, Yasuhiro Take, Tadahiro Kuroda, Paul Bogdan, Radu Marculescu, Hideharu Amano:
Low-latency wireless 3D NoCs via randomized shortcut chips. DATE 2014: 1-6 - [c49]Ikki Fujiwara
, Michihiro Koibuchi, Hiroki Matsutani, Henri Casanova:
Skywalk: A Topology for HPC Networks with Low-Delay Switches. IPDPS 2014: 263-272 - [c48]Radu Marculescu
, Partha Pratim Pande, Deuk Hyoun Heo, Hiroki Matsutani:
Introduction to the special session on "Interconnect enhances architecture: Evolution of wireless NoC from planar to 3D". NOCS 2014: 174-175 - 2013
- [j10]Hao Zhang, Hiroki Matsutani, Yasuhiro Take, Tadahiro Kuroda, Hideharu Amano:
Vertical Link On/Off Regulations for Inductive-Coupling Based Wireless 3-D NoCs. IEICE Trans. Inf. Syst. 96-D(12): 2753-2764 (2013) - [j9]Noriyuki Miura, Yusuke Koizumi, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
:
A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface. IEEE Micro 33(6): 6-15 (2013) - [c47]Hiroki Matsutani, Paul Bogdan
, Radu Marculescu
, Yasuhiro Take, Daisuke Sasaki, Hao Zhang, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano:
A case for wireless 3D NoCs for CMPs. ASP-DAC 2013: 23-28 - [c46]Hao Zhang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Dynamic power on/off method for 3D NoCs with wireless inductive-coupling links. COOL Chips 2013: 1-3 - [c45]Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
:
A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface. COOL Chips 2013: 1-3 - [c44]Yusuke Koizumi, Noriyuki Miura, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
:
Demonstration of a heterogeneous multi-core processor with 3-D inductive coupling links. FPL 2013: 1 - [c43]Noriyuki Miura, Yusuke Koizumi, Eiichi Sasaki, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
:
A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface. Hot Chips Symposium 2013: 1 - [c42]Michihiro Koibuchi, Ikki Fujiwara
, Hiroki Matsutani, Henri Casanova:
Layout-conscious random topologies for HPC off-chip interconnects. HPCA 2013: 484-495 - [c41]Hiroki Matsutani:
Research Challenges on 2-D and 3-D Network-on-Chips. CANDAR 2013: 24-25 - [c40]Daisuke Sasaki, Hao Zhang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
A Routing Strategy for Inductive-Coupling Based Wireless 3-D NoCs by Maximizing Topological Regularity. ICA3PP (2) 2013: 77-85 - [c39]Takahiro Kagami, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Headfirst sliding routing: A time-based routing scheme for bus-NoC hybrid 3-D architecture. NOCS 2013: 1-8 - 2012
- [j8]Yuan He, Hiroki Matsutani, Hiroshi Sasaki, Hiroshi Nakamura:
Adaptive Data Compression on 3D Network-on-Chips. Inf. Media Technol. 7(1): 153-160 (2012) - [j7]Kazutoshi Suito, Rikuhei Ueda, Kei Fujii, Takuma Kogo, Hiroki Matsutani, Nobuyuki Yamasaki:
The Dependable Responsive Multithreaded Processor for Distributed Real-Time Systems. IEEE Micro 32(6): 52-61 (2012) - [c38]Hao Zhang, Hiroki Matsutani, Yasuhiro Take, Tadahiro Kuroda, Hideharu Amano:
Vertical Link On/Off Control Methods for Wireless 3-D NoCs. ARCS 2012: 212-224 - [c37]Hiroki Matsutani, Yuto Hirata, Michihiro Koibuchi, Kimiyoshi Usami, Hiroshi Nakamura
, Hideharu Amano:
A multi-Vdd dynamic variable-pipeline on-chip router for CMPs. ASP-DAC 2012: 407-412 - [c36]Kazutoshi Suito, Kei Fujii, Hiroki Matsutani, Nobuyuki Yamasaki:
Dependable Responsive Multithreaded Processor for distributed real-time systems. COOL Chips 2012: 1-3 - [c35]Yusuke Koizumi, Eiichi Sasaki, Hideharu Amano, Hiroki Matsutani, Yasuhiro Take, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
:
CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnect. FPL 2012: 543-546 - [c34]Yusuke Koizumi, Hideharu Amano, Hiroki Matsutani, Noriyuki Miura, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura
:
Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect. FPT 2012: 293-296 - [c33]Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, D. Frank Hsu, Henri Casanova:
A case for random shortcut topologies for HPC interconnects. ISCA 2012: 177-188 - [c32]Takeo Nakamura, Hiroki Matsutani, Michihiro Koibuchi, Kimiyoshi Usami, Hideharu Amano:
Fine-Grained Power Control Using A Multi-Voltage Variable Pipeline Router. MCSoC 2012: 59-66 - 2011
- [j6]Cisse Ahmadou Dit Adi, Hiroki Matsutani, Michihiro Koibuchi, Hidetsugu Irie, Takefumi Miyoshi, Tsutomu Yoshinaga:
An Efficient Path Setup for a Hybrid Photonic Network-on-Chip. Int. J. Netw. Comput. 1(2): 244-259 (2011) - [j5]Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga:
Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple Predictors. IEEE Trans. Computers 60(6): 783-799 (2011) - [j4]Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura
, Hideharu Amano:
Performance, Area, and Power Evaluations of Ultrafine-Grained Run-Time Power-Gating Routers for CMPs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(4): 520-533 (2011) - [c31]Michihiro Koibuchi, Takafumi Watanabe, Atsushi Minamihata, Masahiro Nakao, Tomoyuki Hiroyasu, Hiroki Matsutani, Hideharu Amano:
Performance Evaluation of Power-Aware Multi-tree Ethernet for HPC Interconnects. ICNC 2011: 50-57 - [c30]Hiroki Matsutani, Yasuhiro Take, Daisuke Sasaki, Masayuki Kimura, Yuki Ono, Yukinori Nishiyama, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano:
A vertical bubble flow network using inductive-coupling for 3-D CMPs. NOCS 2011: 49-56 - [c29]Kei Fujii, Hiroyuki Chishiro, Hiroki Matsutani, Nobuyuki Yamasaki:
Dynamic Voltage and Frequency Scaling for Real-Time Scheduling on a Prioritized SMT Processor. RTCSA (2) 2011: 9-15 - [c28]Masakazu Taniguchi, Hiroki Matsutani, Nobuyuki Yamasaki:
Design and Implementation of On-Chip Adaptive Router with Predictor for Regional Congestion. RTCSA (2) 2011: 22-27 - [c27]Daihan Wang, Michihiro Koibuchi, Tomohiro Yoneda, Hiroki Matsutani, Hideharu Amano:
A Dynamic Link-Width Optimization for Network-on-Chip. RTCSA (2) 2011: 106-108 - [p2]Hiroki Matsutani, Michihiro Koibuchi, Hiroshi Nakamura
, Hideharu Amano:
Run-Time Power-Gating Techniques for Low-Power On-Chip Networks. Low Power Networks-on-Chip 2011: 21-43 - [p1]Hiroki Matsutani, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano:
3-D NoC on Inductive Wireless Interconnect. 3D Integration for NoC-based SoC Architectures 2011: 225-248 - 2010
- [c26]Cisse Ahmadou Dit Adi, Hiroki Matsutani, Michihiro Koibuchi, Hidetsugu Irie, Takefumi Miyoshi, Tsutomu Yoshinaga:
An Efficient Path Setup for a Photonic Network-on-Chip. ICNC 2010: 156-161 - [c25]Yuto Hirata, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
A variable-pipeline on-chip router optimized to traffic pattern. NoCArc@MICRO 2010: 57-62 - [c24]José Miguel Montañana Aliaga
, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano:
Stabilizing Path Modification of Power-Aware On/Off Interconnection Networks. NAS 2010: 218-227 - [c23]Yuri Nishikawa
, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano:
A Deadlock-Free Non-minimal Fully Adaptive Routing Using Virtual Cut-Through Switching. NAS 2010: 431-438 - [c22]Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura
, Hideharu Amano:
Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs. NOCS 2010: 61-68
2000 – 2009
- 2009
- [j3]Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
A Link Removal Methodology for Application-Specific Networks-on-Chip on FPGAs. IEICE Trans. Inf. Syst. 92-D(4): 575-583 (2009) - [j2]Hiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, D. Frank Hsu, Hideharu Amano:
Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network. IEEE Trans. Parallel Distributed Syst. 20(8): 1126-1141 (2009) - [c21]Shotaro Saito, Yoshinori Kohama, Yasufumi Sugimori, Yohei Hasegawa, Hiroki Matsutani, Toru Sano, Kazutaka Kasuga, Yoichi Yoshida, Kiichi Niitsu
, Noriyuki Miura, Tadahiro Kuroda, Hideharu Amano:
MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link. FPL 2009: 6-11 - [c20]Hiroki Matsutani, Michihiro Koibuchi
, Hideharu Amano, Tsutomu Yoshinaga:
Prediction router: Yet another low latency on-chip router architecture. HPCA 2009: 367-378 - [c19]José Miguel Montañana Aliaga
, Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano:
Balanced Dimension-Order Routing for k-ary n-cubes. ICPP Workshops 2009: 499-506 - [c18]Michihiro Koibuchi, Tomohiro Otsuka, Hiroki Matsutani, Hideharu Amano:
An on/off link activation method for low-power ethernet in PC clusters. IPDPS 2009: 1-11 - [c17]Vu Manh Tuan, Naohiro Katsura, Hiroki Matsutani, Hideharu Amano:
Evaluation of a multicore reconfigurable architecture with variable core sizes. IPDPS 2009: 1-8 - [c16]José Miguel Montañana Aliaga, Michihiro Koibuchi, Takafumi Watanabe, Tomoyuki Hiroyasu, Hiroki Matsutani, Hideharu Amano:
An On/Off Link Activation Method for Power Regulation in InfiniBand. PDPTA 2009: 289-295 - 2008
- [c15]Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Daihan Wang:
Run-time power gating of on-chip routers using look-ahead routing. ASP-DAC 2008: 55-60 - [c14]Daihan Wang, Hiroki Matsutani, Hideharu Amano, Michihiro Koibuchi:
A link removal methodology for Networks-on-Chip on reconfigurable systems. FPL 2008: 269-274 - [c13]Hiroki Matsutani, Michihiro Koibuchi, D. Frank Hsu, Hideharu Amano:
Three-Dimensional Layout of On-Chip Tree-Based Networks. ISPAN 2008: 281-288 - [c12]Michihiro Koibuchi, Hiroki Matsutani, Hideharu Amano, Timothy Mark Pinkston:
A Lightweight Fault-Tolerant Mechanism for Network-on-Chip. NOCS 2008: 13-22 - [c11]Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang, Hideharu Amano:
Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks. NOCS 2008: 23-32 - 2007
- [j1]Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
A Port Combination Methodology for Application-Specific Networks-on-Chip on FPGAs. IEICE Trans. Inf. Syst. 90-D(12): 1914-1922 (2007) - [c10]Daihan Wang, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
A Temporal Correlation Based Port Combination Methodology for Networks-on-chip on Reconfigurable Systems. FPL 2007: 383-388 - [c9]Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Tightly-Coupled Multi-Layer Topologies for 3-D NoCs. ICPP 2007: 75 - [c8]Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Performance, Cost, and Energy Evaluation of Fat H-Tree: A Cost-Efficient Tree-Based On-Chip Network. IPDPS 2007: 1-10 - 2006
- [c7]Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
A Virtual-Channel Free Mapping for Application-Specific On-Chip Torus Networks. PDCS 2006: 24-31 - [c6]Daihan Wang, Hiroki Matsutani, Masato Yoshimi, Michihiro Koibuchi, Hideharu Amano:
A Parametric Study of Scalable Interconnects on FPGAs. ERSA 2006: 130-135 - [c5]Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Enforcing Dimension-Order Routing in On-Chip Torus Networks Without Virtual Channels. ISPA 2006: 207-218 - 2005
- [c4]Yohei Hasegawa, Shohei Abe, Hiroki Matsutani, Hideharu Amano, Kenichiro Anjo, Toru Awashima:
An Adaptive Cryptographic Accelerator for IPsec on Dynamically Reconfigurable Processor. FPT 2005: 163-170 - [c3]Ryuji Wakikawa, Hiroki Matsutani, Rajeev Koodli, Anders Nilsson, Jun Murai:
Mobile Gateways for Mobile Ad-Hoc Networks with Network Mobility Support. ICN (2) 2005: 361-368 - [c2]Hiroki Matsutani, Michihiro Koibuchi, Yutaka Yamada, Akiya Jouraku
, Hideharu Amano:
Non-Minimal Routing Strategy for Application-Specific Networks-on-Chips. ICPP Workshops 2005: 273-280 - [c1]Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano:
Destination Bundle: A Routing Table Reduction Technique for Distributed Routing on Dependable Networks-on-Chips. PDPTA 2005: 1343-1349
Coauthor Index
![](https://dblp.org/img/cog.dark.24x24.png)
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from ,
, and
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and
to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from .
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-09-02 00:12 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint